Browse Prior Art Database

Synonym Avoidance Cache

IP.com Disclosure Number: IPCOM000120872D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 5 page(s) / 218K

Publishing Venue

IBM

Related People

Brenza, JG: AUTHOR

Abstract

The occurrence and cause of synonym cache lines in a digital computer cache buffer are well known in the state of the art. In general, a synonym line is located in a cache position different from the one which is derived from the requesting address. Since the synonym line stores the latest copy of the requested data, its true location in the cache must be discovered. The data access to the cache may then be completed correctly at the synonym address for a conventional cache. This discovery and re-access involves significant hardware expense and an additional access penalty to search the cache directory to discover the synonym, and to restart the cache with the synonym address.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 32% of the total text.

Synonym Avoidance Cache

      The occurrence and cause of synonym cache lines in a
digital computer cache buffer are well known in the state of the art.
In general, a synonym line is located in a cache position different
from the one which is derived from the requesting address.  Since the
synonym line stores the latest copy of the requested data, its true
location in the cache must be discovered.  The data access to the
cache may then be completed correctly at the synonym address for a
conventional cache.  This discovery and re-access involves
significant hardware expense and an additional access penalty to
search the cache directory to discover the synonym, and to restart
the cache with the synonym address.

      This article describes a cache structure for a general-purpose
digital computer which avoids the need to provide special hardware to
first discover and then access synonym lines with synonym addresses
in the cache.
CACHE OPERATIONAL DESCRIPTION

      Definition: Throughout this description, the term "Logical
Address" is used.  This is intended to mean any one of a variety of
machine-generated addresses.  It may be a real address (DAT off) or a
virtual address (DAT on).  It may be an instruction address, or an
instruction operand address.  It may be a real address due to special
hardware references to main memory tables (e.g., segment and page
tables), etc.

      The figure is a data flow of the Logical Cache with Synonym
Avoidance.  This data flow is composed of three subsystems:
 (1) Central Processing Unit (CPU) Subsystem.  This subsystem in a
conventional digital processor with instruction units, execution
units, etc., normally associated with a unit processor (UP).
Multiple CPUs (not shown) interconnect via the SCE subsystem.
 (2) L1 Cache Subsystem.  This subsystem, which is private to each
CPU, contains a set of arrays and controls, defined below, to
implement a "Logical Cache".  Such a cache responds directly to data
requests based on "logical addresses" without need for prior address
translation.
 (a) L1 Cache.  This is the cache data buffer and is addressed with a
"Logical Address" which may be real or virtual as determined by the
CPU request.
           (b) L1 Logical Directory.  This directory stores an entry
for each cache line in a congruence position determining the "logical
address" which first requested the data from main memory.  This
address encodes the "principal class" for each line of data in cache.
If a line of data is valid in cache, but not locatable at a
"principal class" address position, such a line is thus located in
cache at one (of many) "synonym class" address position.  This occurs
when a subsequent cache request to a cache line is made with a
different logical address than the one which first determined its
positions.  Note that there are special cases where a principal class
line and a synonym class line have the same physical cache
congruence, but d...