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Browse Prior Art Database

Means for Improving the Performance of Static Address Decoders

IP.com Disclosure Number: IPCOM000120883D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 76K

Publishing Venue

IBM

Related People

Buettner, S: AUTHOR [+4]

Abstract

This article describes a means for improving the performance of a static address decoder by using additional wiring between the logic books (logic circuits) from which the decoder is built. A standard static address decoder constructed using eight three-way AND gates 10a-h is shown in Fig. 1. The three-bit addressing is supplied with true signals on input lines 1t, 2t and 3t and with complement signals on input lines 1c, 2c and 3c. The input lines are connected to the inputs AO, A1 and A2 to the AND gates 10a-h as shown in Fig. 1.

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Means for Improving the Performance of Static Address Decoders

      This article describes a means for improving the
performance of a static address decoder by using additional wiring
between the logic books (logic circuits) from which the decoder is
built.  A standard static address decoder constructed using eight
three-way AND gates 10a-h is shown in Fig. 1.  The three-bit
addressing is supplied with true signals on input lines 1t, 2t and 3t
and with complement signals on input lines 1c, 2c and 3c.  The input
lines are connected to the inputs AO, A1 and A2 to the AND gates
10a-h as shown in Fig. 1.

      The internal circuit of any one of the AND gates 10a-h is shown
in Fig. 2.  It consists of three p-type FETs 120a-c, the gate of each
of which is connected to one of the inputs A0, A1 of A2, and three
n-type FETs 110a-c, the gate of each of which is connected to one of
the inputs A0, A1 or A2.  The performance of the three-way AND gates
10a-h is mainly determined by the discharge of the output node 20
through the three n-type FETs 110a-c arranged in series. The
performance can be drastically improved by connecting the internal
nodes X and Y of the logic book to the logically identical internal
nodes of the other books of the decoder.  This is shown in Fig. 3.
For simplification, only the n-type FETs 110a-c, 210a-c, 310a-c,
410a-c, 510a-c, 610a-c, 710a-c and 810a-c of the eight AND gates
10a-h are shown.

      It can be seen in Fig. 3 that the discharg...