Browse Prior Art Database

Full-Swing BICMOS Circuit Family

IP.com Disclosure Number: IPCOM000120909D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 70K

Publishing Venue

IBM

Related People

Puri, YK: AUTHOR [+2]

Abstract

BICMOS (bipolar-CMOS) circuits which can develop the full CMOS voltage levels are useful because they can be intermixed with standard CMOS logic gates. This approach allows high-speed BICMOS response where needed and high-density CMOS where circuit performance is not as critical. The NAND circuit shown in the figure uses bipolar devices to achieve the performance associated with BICMOS logic, and it also has full CMOS output levels.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 54% of the total text.

Full-Swing BICMOS Circuit Family

      BICMOS (bipolar-CMOS) circuits which can develop the full
CMOS voltage levels are useful because they can be intermixed with
standard CMOS logic gates.  This approach allows high-speed BICMOS
response where needed and high-density CMOS where circuit performance
is not as critical.  The NAND circuit shown in the figure uses
bipolar devices to achieve the performance associated with BICMOS
logic, and it also has full CMOS output levels.

      When one or both of the inputs is a down-level, the base
voltage of Q2 is high and the bipolar device Q1 is cut off because T7
is conducting.  Since Q2 is an emitter/follower it is able to drive
capacitive output loads very well, and the output rise time will be
short. Transistor Q2 will cease to drive when the output reaches one
VBE drop (approximately 0.7 V) below the power supply level; this
level is insufficient to keep succeeding stages from leaking.  The
final level of VDD is achieved by the CMOS inverter pair.  The final
charging rate can be less than the initial rate, so the devices
composing the CMOS inverters need not be very large.

      If both the inputs are up levels, the base of transistor Q2 is
pulled to ground, cutting off Q2.  Also, the path through T5 and T6
conducts driving Q1 on.  The load capacitance will be rapidly
discharged by Q1 to a level which is one VBE drop (approximately 0.7
V) above ground. The final discharge to ground is again accomplished
by th...