Browse Prior Art Database

Building a Logical Image of Cache

IP.com Disclosure Number: IPCOM000120911D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 45K

Publishing Venue

IBM

Related People

Clark, BD: AUTHOR [+5]

Abstract

Disclosed is a scheme for a logical apportionment of cache in a cached control unit.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 80% of the total text.

Building a Logical Image of Cache

      Disclosed is a scheme for a logical apportionment of
cache in a cached control unit.

      Cache divides into segments (16k byte areas), referenced
through entries in a directory structure, located in cache.
According to host input, at cache initialization time microcode
assigns segments to contain either structures or user data.  If the
segments' directory entry holds this segment assignment indication
(as it does in previous designs), microcode (and hardware) must write
every directory entry into cache at initialization time.  The time
necessary for these excessive cache writes is a problem. This article
describes a solution to that problem.

      This invention builds a structure in the joint array structure
(JAS) to hold the segment assignment indication. This solution
creates, at initialization time, a 'virtual' image of cache in the
JAS.  In this scheme cache is logically just a sequential list of
pairs, corresponding to a sequential ordering of cache.  Each pair is
a count (the number of similar contiguous segments) and a label
(indicating assignment).  Note here that this solution allows any
number of contiguous groupings and also any number of descriptions of
segments simply by choosing a new unique label.  Now, at free lists
build time, code queries this logical map.  A function outputs the
label indicating segment assignment.  Another function allows
decrementing the count to logically point to the nex...