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Reliable High Density Raw Card Test Method

IP.com Disclosure Number: IPCOM000120912D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 44K

Publishing Venue

IBM

Related People

Dameron, ED: AUTHOR [+2]

Abstract

Current printed circuit board (PCB) designs are limited by the diameter of the contact probes used to test the PCB. Surface mount pads, plated through holes (PTH), and contact tabs are located to allow testable circuits at both the raw and assembled PCB manufacturing facilities. This limitation dictates designs which either use significant amount of PCB real estate, or complex chip integration. Also, the current test heads cannot reliably make contact with the test probes and/or test sites due to contamination. The test heads provide no wiping of the contacted surface which reduces its ability to penetrate any oxide on the test surface.

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Reliable High Density Raw Card Test Method

      Current printed circuit board (PCB) designs are limited by the
diameter of the contact probes used to test the PCB. Surface mount
pads, plated through holes (PTH), and contact tabs are located to
allow testable circuits at both the raw and assembled PCB
manufacturing facilities.  This limitation dictates designs which
either use significant amount of PCB real estate, or complex chip
integration.  Also, the current test heads cannot reliably make
contact with the test probes and/or test sites due to contamination.
The test heads provide no wiping of the contacted surface which
reduces its ability to penetrate any oxide on the test surface.

      This method documents a technique for making contact with raw
PCBs by replacing the current contact test probes with a new
mechanism based on linearly conductive material (LCM) and a master
test board.  The LCM consists of nonwoven, conductive fibers
impregnated in an insulating, deformable media.  This material is
made such that it can provide electrical contact between two circuit
patterns, one on the PCB being tested and the other being the master
test board.  The master test board is designed so no circuits are
present at the interface with the LCM.   A PTH via is placed at each
point being tested on both PCBs.  The size of the PTH would be a
function of the density of the circuits being tested.  Also, the LCM
would provide limited contact wiping as the material i...