Browse Prior Art Database

Extracting Timing From Rank During Simulation

IP.com Disclosure Number: IPCOM000120915D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 23K

Publishing Venue

IBM

Related People

Becker, MG: AUTHOR [+2]

Abstract

Disclosed is an idea to extract final timing during simulation based on the rank ordering of the model.

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This is the abbreviated version, containing approximately 100% of the total text.

Extracting Timing From Rank During Simulation

      Disclosed is an idea to extract final timing during simulation
based on the rank ordering of the model.

      Using the rank ordering concept discussed in Research
Disclosure, #31726, September, 1990, in which each logic node is
scheduled on a level just after its last input is available, it is
possible to use the simulation to acquire the time within a cycle
when the node will be set to its final value.  This time will be the
level on which the node is scheduled with each level being an
increment in an A/B unit delay simulation machine cycle.  This idea
loses glitch information.

      Disclosed anonymously.