Browse Prior Art Database

Protecting a CMOS Device Under Test When Its Power is Off

IP.com Disclosure Number: IPCOM000120917D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 45K

Publishing Venue

IBM

Related People

Bordovsky, JS: AUTHOR [+4]

Abstract

Disclosed is a circuit for protecting a CMOS device under test when its power is turned off. (Image Omitted)

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Protecting a CMOS Device Under Test When Its Power is Off

      Disclosed is a circuit for protecting a CMOS device under test
when its power is turned off.

                            (Image Omitted)

      Before the bias voltage for a CMOS device under test is stable,
tester driver and/or receiver circuits may source or sink enough
current to damage the CMOS device.  The tester interface circuit may
use bipolar drivers and receivers to interface to a CMOS device under
test.  Although the tester drivers can be tri-stated, they could
still damage a CMOS device which is not powered on.  Also, the
bipolar receivers could damage a CMOS device which is not powered on.

      The tester needs to be able to plug into a machine under test
which may or may not be powered on.  The tester interface circuit
senses power on the CMOS device under test and turns power on and off
to the tester bipolar drivers and receivers.  The CMOS device is
protected since no power is supplied to the tester drivers and
receivers until the CMOS device is powered on.

      Disclosed anonymously.