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Low Resistivity Stack for Dual Doped Polysilicon Gate Electrode

IP.com Disclosure Number: IPCOM000120927D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 51K

Publishing Venue

IBM

Related People

Nesbit, LA: AUTHOR [+3]

Abstract

A stack of materials and a process to deposit them is described which produces a low resistivity gate electrode while preserving gate oxide integrity, is consistent with dual work function polysilicon, and confines dopants to material layers initially containing them.

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This is the abbreviated version, containing approximately 99% of the total text.

Low Resistivity Stack for Dual Doped Polysilicon Gate Electrode

      A stack of materials and a process to deposit them is described
which produces a low resistivity gate electrode while preserving gate
oxide integrity, is consistent with dual work function polysilicon,
and confines dopants to material layers initially containing them.

      Referring to the figure, dual work function polysilicon 2 is
deposited by standard chemical vapor deposition on a substrate
comprised of gate dielectric 4 on silicon wafer 6. Titanium nitride
(TiN) 8 is a fair conductor and a good barrier to motion of dopants
into or out of polysilicon 2. TiN 8 may be deposited by sputtering in
an argon and nitrogen gas mixture.  Silicon rich titanium disilicide
(TiSi2) 10 is a good conductor, particularly after annealing, which
may be deposited by sputtering a silicon rich TiSi2 (or Ti + Si of
the silicide proportions) target in argon gas.  Insulating protective
overlayer silicon nitride (Si3N4) 12 may also be sputter deposited
from a silicon target in argon and nitrogen.  Layers 8, 10, and 12
may be deposited in a multi-station sputtering tool without exposure
to atmosphere between process steps.

      Sputtering these materials, unlike chemical vapor deposition of
some of them, does not occlude hydrogen in the films.  Presence of
hydrogen substantially increases diffusion rate of dopants from
polysilicon 2 through gate dielectric 4 into silicon substrate 6.

      Disclosed ano...