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Browse Prior Art Database

Low Profile Chip Package

IP.com Disclosure Number: IPCOM000120928D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 32K

Publishing Venue

IBM

Related People

Caporale, RJ: AUTHOR [+2]

Abstract

A method for mounting integrated circuit chips having a relatively small number of input/output connections wherein reflow solder connection is made from circuit chip to a silicon or ceramic substrate and from that substrate to a next assembly level, e.g., card or board, results in a low profile, low inductance, low cost assembled card.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Low Profile Chip Package

      A method for mounting integrated circuit chips having a
relatively small number of input/output connections wherein reflow
solder connection is made from circuit chip to a silicon or ceramic
substrate and from that substrate to a next assembly level, e.g.,
card or board, results in a low profile, low inductance, low cost
assembled card.

      Referring to the figure, circuit chip 2 is connected to ceramic
or silicon substrate 4 via reflowed solder joints 6. Connections from
solder joints 6 to much larger reflowed solder ball connections 8 is
made by circuitry on the surface of substrate 4 (not shown).  Solder
ball connections 8 are reflowed to circuitry 10 on card 12.

      Thus, with single sided wiring on substrate 4, no through hole
or pin connections, and no module assembly, a low cost second level
package is achieved which has a low profile resulting in low circuit
inductance.

      Disclosed anonymously.