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Browse Prior Art Database

Full Adder

IP.com Disclosure Number: IPCOM000120942D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 26K

Publishing Venue

IBM

Related People

Erlebacher, SA: AUTHOR [+3]

Abstract

The figure shows a FA (full adder) using current switch emitter follower logic with essentially one stage of delay. The two-stage path consists of two inverters that can match the speed of the longest single stage path in a custom wired macro. The FA inputs and outputs are all true or all complemented (shown in brackets).

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Full Adder

      The figure shows a FA (full adder) using current switch emitter
follower logic with essentially one stage of delay. The two-stage
path consists of two inverters that can match the speed of the
longest single stage path in a custom wired macro.  The FA inputs and
outputs are all true or all complemented (shown in brackets).

      Disclosed anonymously.