Browse Prior Art Database

Expansion of LOCST to Include OCDs And OCRs

IP.com Disclosure Number: IPCOM000120948D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 58K

Publishing Venue

IBM

Related People

LeBlanc, JJ: AUTHOR [+2]

Abstract

In LOCST, the shift registers in an LSSD design are configured, during self test mode, such that each is fed from a pseudo random pattern generator (PRPG) and each feeds into a signature analyzer to compress the results. During such test, however, the Primary Inputs (PIs) are disabled and the Primary Outputs (POs) are ignored. The PIs are disabled because, in multichip modules (MCMs) or in the system, the chips feeding this chip under test may not be controllable, hence the PIs could be at a random state, thus invalidating the test. POs are ignored since in the MCM or system environment, the state of these pins is not observable. The result of this handling of PIs and POs is that these pins and any logic solely feeding these pins, is not tested during self test, thereby creating a quality exposure.

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Expansion of LOCST to Include OCDs And OCRs

      In LOCST, the shift registers in an LSSD design are configured,
during self test mode, such that each is fed from a pseudo random
pattern generator (PRPG) and each feeds into a signature analyzer to
compress the results.  During such test, however, the Primary Inputs
(PIs) are disabled and the Primary Outputs (POs) are ignored.  The
PIs are disabled because, in multichip modules (MCMs) or in the
system, the chips feeding this chip under test may not be
controllable, hence the PIs could be at a random state, thus
invalidating the test.  POs are ignored since in the MCM or system
environment, the state of these pins is not observable.  The result
of this handling of PIs and POs is that these pins and any logic
solely feeding these pins, is not tested during self test, thereby
creating a quality exposure.

      The solution is to configure PIs and POs so that they become
Common I/Os (CIOs).  This then creates a path through these pins back
into the chip performing self test and enables their test.  This
reconfiguration is done as follows:
      1.   Pins that are purely inputs for system use must be
redesigned into common I/O.  The logic must be implemented such that,
when in self test mode, the added off chip driver is forced into the
drive (non-tristate) mode and is fed from any SRL. Since each SRL is
set by the PRPG during self test, this allows the output and the
corresponding input receiver to be sti...