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PNP Level Shifter/Regulator

IP.com Disclosure Number: IPCOM000120951D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 27K

Publishing Venue

IBM

Related People

Montegari, FA: AUTHOR

Abstract

The PNP Level Shifter/Regulator depicted in the Figure produces a regulated voltage drop in a negative direction and can be designed to deliver a drop of from .2 volts to .7 volts below Vcc . Current flows from Vcc into the emitter of T1, then out of its collector into the output node and also through resistor divider R1 and R2 into Vee. The base of T1 is connected to the junction of R1 and R2 whose values are chosen to produce the desired output level, Vout = Vcc - Vbe + Vri. R2 is designed to pull a bias current of typically one milliampere. When load current pulls the output node down, feedback through R1 to the base of T1 turns T1 on harder, thus regulating the output voltage. (Image Omitted)

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PNP Level Shifter/Regulator

      The PNP Level Shifter/Regulator depicted in the Figure produces
a regulated voltage drop in a negative direction and can be designed
to deliver a drop of from .2 volts to .7 volts below Vcc .  Current
flows from Vcc into the emitter of T1, then out of its collector into
the output node and also through resistor divider R1 and R2 into Vee.
The base of T1 is connected to the junction of R1 and R2 whose values
are chosen to produce the desired output level, Vout = Vcc - Vbe +
Vri.  R2 is designed to pull a bias current of typically one
milliampere.  When load current pulls the output node down, feedback
through R1 to the base of T1 turns T1 on harder, thus regulating the
output voltage.

                            (Image Omitted)

      Disclosed anonymously.