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Image Scaling With Two-Dimensional Memory Arrays

IP.com Disclosure Number: IPCOM000120969D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 6 page(s) / 318K

Publishing Venue

IBM

Related People

Vogelsberg, RE: AUTHOR

Abstract

During the printing of image data, it is often necessary to convert the input image from one print resolution to another, e.g., from 300 bits/inch scanner input to 240 bits/inch for printer output, or to scale the image to another size to fit within an output area. Performing these conversions within a processor is very slow because the processing of each bit in the image requires the execution of many instructions. This design provides a general hardware facility which allows the scaling or resolution conversion of images to be done much faster than can be accomplished with a processor alone.

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Image Scaling With Two-Dimensional Memory Arrays

      During the printing of image data, it is often necessary
to convert the input image from one print resolution to another,
e.g., from 300 bits/inch scanner input to 240 bits/inch for printer
output, or to scale the image to another size to fit within an output
area.  Performing these conversions within a processor is very slow
because the processing of each bit in the image requires the
execution of many instructions.  This design provides a general
hardware facility which allows the scaling or resolution conversion
of images to be done much faster than can be accomplished with a
processor alone.

      This design makes use of an intelligent set of special-purpose
DMA devices, two banks of registers or memory (organized into two-
dimensional arrays), and a set of unique hardware and associated
control registers to scale or to convert the effective resolution of
bit mapped image data.  As an additional feature, the image may also
be rotated through any increments of 90 degrees.  The hardware can be
programmed to accept a wide range of input image sizes, scale
factors, or rotations.  Once programmed, the hardware is designed to
operate independently from the system processor while carrying out
the image scaling and rotation.  The hardware performs these
functions an order of magnitude faster than can be done by the
processor alone.

      The input image is scaled (or the resolution is converted) by
replicating or deleting rows and columns of bits.  The scaling
operations are controlled by a set of hardware registers which
specify which rows and columns of the input image are to be
replicated or deleted.  Four registers are sufficient to specify all
the commonly required resolution conversations and the majority of
the scaling factors.  If greater scaling precision is required,
additional registers may be added to the hardware or multiple passes
of the image may be made through the hardware.

      Three registers specify which rows and columns of the input
image are to be deleted or added.  A fourth register contains a
replication multiplier associated with the first of the three
registers.  This multiplier is used to indicate that the rows and
columns specified are to be replicated more than once or that more
than one row and column is to be deleted for each of the specified
ones.  Table 1 contains a tabulation of the various register settings
that can be used to perform resolution conversions from any of the
ten standard input resolutions to resolutions of 240, 480, or 600
bits/inch.  The equivalent scale factors are also shown. For example,
if an input image resolution of 300 bits/inch is to be converted to
an output image resolution of 240 bits/inch, then every fifth row and
every fifth column of the input image will be deleted.  This is
equivalent to reducing the scale of the input image by a factor of
0.8.  Similar tables can be created for other cases...