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Reduced Memory Control Circuitry in an Sram Sequential Memory

IP.com Disclosure Number: IPCOM000120978D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 86K

Publishing Venue

IBM

Related People

Hennet, PP: AUTHOR [+4]

Abstract

Disclosed is a control circuitry design that reduces the circuitry necessary for building a high-speed sequential memory system out of low-speed Static Random Access Memory (SRAM) chips.

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This is the abbreviated version, containing approximately 60% of the total text.

Reduced Memory Control Circuitry in an Sram Sequential Memory

      Disclosed is a control circuitry design that reduces the
circuitry necessary for building a high-speed sequential memory
system out of low-speed Static Random Access Memory (SRAM) chips.

      Fig. 1 provides an organization of low-speed SRAM memory that
can be used to capture high-speed sequential data.  By placing n
high- speed buffers (registers) in front of n slow speed memory
systems, high-speed input data can be stored in the slow-speed memory
systems.  Fig. 1 assumes n is 16 and that the input data arrives
every 8 nanoseconds. Each memory group receives data every 8 X 16 =
128 nanoseconds. By using slow speed (assume 70 nanosecond SRAM), the
memory system is able to capture sequential data arriving every 8
nanoseconds.

      The new and novel feature of this article is the ability to use
SRAM memory in such a way that only eight independent memories can
accomplish the same function.  This means that the control circuitry
for address, chip select, and write enable are cut in half.

      This reduction of circuitry is accomplished by taking advantage
of the property of SRAM memory that only requires the data to be
available during approximately the last half of the write cycle.
Fig.  2 illustrates this property for a 70-nanosecond SRAM.  The
input data is latched into the 16 input registers in a round-robin
order.  The data can arrive at 8 nanosecond intervals or slower.
Assume...