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Address Generation Time Saving Circuitry for an SRAM Sequential Memory

IP.com Disclosure Number: IPCOM000120980D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 5 page(s) / 139K

Publishing Venue

IBM

Related People

Hennet, PP: AUTHOR [+4]

Abstract

Disclosed is circuitry to save time in the circuitry that must generate the next sequential address for a sequential Static Random Access Memory (SRAM) system. In a sequential memory system there comes a time when the address to the memory must be changed in between two successive memory writes. If this time is large, then the speed of the memory system must be slowed down so that the address is stable prior to the next sequential write. This article demonstrates a unique method of reducing the time to generate the next sequential address.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Address Generation Time Saving Circuitry for an SRAM Sequential Memory

      Disclosed is circuitry to save time in the circuitry that
must generate the next sequential address for a sequential Static
Random Access Memory (SRAM) system.  In a sequential memory system
there comes a time when the address to the memory must be changed in
between two successive memory writes.  If this time is large, then
the speed of the memory system must be slowed down so that the
address is stable prior to the next sequential write.  This article
demonstrates a unique method of reducing the time to generate the
next sequential address.

      Fig. 1 provides an organization of low-speed SRAM memory that
can be used to capture high-speed sequential data.  By placing n
high- speed buffers (registers) in front of n slow-speed memory
systems, high-speed input data can be stored in the slow-speed memory
systems.  Fig. 1 assumes n is 16 and that the input data arrives
every 8 nanoseconds. Each memory group receives data every 8 X 16 =
128 nanoseconds. By using slow speed (assume 70 nanosecond SRAM), the
memory system is able to capture sequential data arriving every 8
nanoseconds.

      The new and novel feature of this article is the ability to
increment the address for the memory without having to wait for the
time it takes a counter to increment by one.

      Fig. 2 represents the address values that must be in the
address register of each memory group.  Address "0" must be latched
into the respective sixteen memory groups.  Then address "1" must be
latched in during the next sixteen write cycles.  Assume that there
is an address register associated with each memory group.  This
address register must be valid for the entire write cycle.

     ...