Browse Prior Art Database

Glitchless Oscillator Switch for High Reliability

IP.com Disclosure Number: IPCOM000120984D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 4 page(s) / 146K

Publishing Venue

IBM

Related People

Griess, KR: AUTHOR [+2]

Abstract

Disclosed is a method to improve the reliability of system clock generation by duplicating or triplicating the most failure prone component, generally the primary oscillator, and provide a way of transparently switching to the good oscillator(s) when one fails. This invention is based on using a Phase-Locked Loop Frequency Synthesizer (PLLFS) as a buffer between the system clock (Fout) and a set of redundant or triply redundant oscillators, as shown in Figs. 1 and 3. Fig. 1 is discussed first and will be referred to as Approach 1 while Fig. 3 will be referred to as Approach 2.

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Glitchless Oscillator Switch for High Reliability

      Disclosed is a method to improve the reliability of
system clock generation by duplicating or triplicating the most
failure prone component, generally the primary oscillator, and
provide a way of transparently switching to the good oscillator(s)
when one fails. This invention is based on using a Phase-Locked Loop
Frequency Synthesizer (PLLFS) as a buffer between the system clock
(Fout) and a set of redundant or triply redundant oscillators, as
shown in Figs. 1 and 3.  Fig. 1 is discussed first and will be
referred to as Approach 1 while Fig. 3 will be referred to as
Approach 2.  In Approach 1, which is a modified version of the
"standby sparing" method presented in [1], the PLLFS acts as a high
inertia "flywheel" to smooth out any glitch caused by the
asynchronous switching from Oscillator A (OSC A) to Oscillator B (OSC
B) when a failure is detected on OSC A. The flywheel behavior is
accomplished by:
      1.   Ensuring that the frequency of the reference oscillators
(A and B) are greater than a factor of 10 faster than the frequency
of the divide-by-M clock entering the phase detector of the PLLFS.
This is accomplished by making M at least 10.  An extra counter P can
be added ahead of the M counter to provide added "leverage".  The
size of P will be limited by what the desired Fout is and what the
maximum multiplication factor (N/M) of the PLLFS is.
      2.   Choosing the response time of the PLL loop filter to be
100 to 1000 times slower than the cycle time of the divide-by-M
clock.  This is compatible with criteria for maximizing short term
clock stability also.  The response time is proportional to 1/Wn,
where Wn is the natural frequency of the loop.

      Since pulses from the divide-by-M counter will be produced
every PxM cycles of Fr',  switching from OSC A to OSC B will result
in the next divide-by-M pulse being advanced or delayed by at most
1/2 cycle of OSC A(B).  Figs. 2A and 2B show worst-case scenarios of
Fr' as it is switched from OSC A to OSC B.

      This temporay shift of the divide-by-M pulse with respect to
the divide-by-N pulse will result in an error voltage to be
integrated by the loop filter in an attempt to change the system
clock frequency.  However, since the shift represents such...