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Browse Prior Art Database

High Density Direct Chip Attach Substrate Manufacturing Process

IP.com Disclosure Number: IPCOM000120997D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 77K

Publishing Venue

IBM

Related People

Austenfeld, RS: AUTHOR [+4]

Abstract

Disclosed is a process flow for the fabrication of a 4S/2P structure by the novel method illustrated in Fig. 1. The starting material is copper or copper-invar-copper with etched clearance holes. Prepreg material consisting of FR4/Upilex*/FR4 is then laminated to either side of the perforated power core. During lamination, the clearance holes are filled with the FR4 resin as shown in Fig. 1a. One side of the structure shown in Fig. 1a is circuitized using the subtractive method. This constitutes the S2 signal layer. Two such structures are then laminated, back-to-back, using a FR4/Upilex/FR4 sticker sheet. The resulting composite is shown in Fig. 1b. We now have S2 buried the composite.

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High Density Direct Chip Attach Substrate Manufacturing Process

      Disclosed is a process flow for the fabrication of a
4S/2P structure by the novel method illustrated in Fig. 1.  The
starting material is copper or copper-invar-copper with etched
clearance holes.  Prepreg material consisting of FR4/Upilex*/FR4 is
then laminated to either side of the perforated power core.  During
lamination, the clearance holes are filled with the FR4 resin as
shown in Fig. 1a. One side of the structure shown in Fig. 1a is
circuitized using the subtractive method.  This constitutes the S2
signal layer.  Two such structures are then laminated, back-to-back,
using a FR4/Upilex/FR4 sticker sheet.  The resulting composite is
shown in Fig. 1b.  We now have S2 buried the composite.  The
composite is then drilled using a 4 mil drill bit, seeded, plated and
etched (using standard techniques) to create the S1 and S4 signal
layers. The overall composite, which is shown in Fig. 1c, is a 4S/2P
structure with plated through holes.  There are no power vias in this
structure.  Instead, through holes which contact the power planes are
also drilled and plated.  There are two methods for direct chip
attach on this structure. Method 1 is to etch C4 pads on the S1 layer
which are connected to the PTHs followed by gold cap lamination as
practiced for the HDC technology.  The gold caps with top surface
metallurgy then constitute the C4 pads.  Such caps are also shown in
Fig. 1c.

      Th...