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High-Density Read-Only Store Cell

IP.com Disclosure Number: IPCOM000121010D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Klara, WS: AUTHOR [+2]

Abstract

This article describes a method of achieving a high density Read-Only Store (ROS) cell on a chip which can be fabricated in less than six sq. micrometers. Fig. 1 illustrates a partial cross section of an array matrix in which the cell topology is structured. There are m word lines shown in the vertical direction and n bit lines distributed horizontally. The word lines are all connected to every base in the bit direction. The bit lines are connected to the emitter of those transistors where you want "1" data. Where a connection is not made, you have "0" data. The bit lines are connected to an emitter of a current switch transistor (not shown) forming a current switch with all transistors on a common bit line. Other connections are possible; the current switch is only an example.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 70% of the total text.

High-Density Read-Only Store Cell

      This article describes a method of achieving a high
density Read-Only Store (ROS) cell on a chip which can be fabricated
in less than six sq. micrometers.  Fig. 1 illustrates a partial cross
section of an array matrix in which the cell topology is structured.
There are m word lines shown in the vertical direction and n bit
lines distributed horizontally. The word lines are all connected to
every base in the bit direction.  The bit lines are connected to the
emitter of those transistors where you want "1" data.  Where a
connection is not made, you have "0" data.  The bit lines are
connected to an emitter of a current switch transistor (not shown)
forming a current switch with all transistors on a common bit line.
Other connections are possible; the current switch is only an
example.

      The fabrication of the chip requires the deposition of a
blanket subcollector which forms the collectors of the devices to be
made.  The topology of the device structure is shown in Fig. 2.  An
opening in the isolation is made for every possible location of a
device in the array matrix.  P poly is then deposited over the whole
chip etched into strips that cover the openings made down to the N-
substrate.  A heat cycle is performed to form in the base. The
polysilicon is then coated with metal, forming a low resistance
polycide layer.  This layer then connects all the bases in the row
together.

      Two methods of personalizatio...