Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Last Event Triggered Pulse Generator

IP.com Disclosure Number: IPCOM000121033D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 82K

Publishing Venue

IBM

Related People

Klara, W: AUTHOR [+2]

Abstract

Disclosed is the Last Event Pulse Generator circuit which produces a pulse which may be retriggered at any time. The initial pulse is triggered by an input pulse that is supplied by the user. If another pulse occurs during the pulse cycle, the internal delay element of the pulse generator is reset by the leading edge of the input pulse. The net result is a pulse which starts during the leading edge of the first input pulse and ends a fixed time after the falling edge of the last input pulse.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 86% of the total text.

Last Event Triggered Pulse Generator

      Disclosed is the Last Event Pulse Generator circuit which
produces a pulse which may be retriggered at any time.  The initial
pulse is triggered by an input pulse that is supplied by the user.
If another pulse occurs during the pulse cycle, the internal delay
element of the pulse generator is reset by the leading edge of the
input pulse. The net result is a pulse which starts during the
leading edge of the first input pulse and ends a fixed time after the
falling edge of the last input pulse.

      The pulse generator is shown in Fig. 1 on the following page.
When an input occurs at the base of T1, the OUTX node will rise to
an up level.  This latches the pulse generator and causes the OUT
node to go to an up level.  The TRISE transistor keeps the capacitive
delay element charged for as long as the input pulse is an up level.
The TIN1 transistor tries to discharge the capacitive net, but the
capacitive net will remain charged as long as TRISE is on.  When the
input pulse goes to a down level the capacitive net will slowly
discharge.  However, if another input pulse occurs, the capacitive
net will quickly recharge.

      In Fig. 2 there are input pulses that occur at 1, 2, and 5
ns. The first input pulse initiates the first output pulse.  The
second input pulse resets the pulse generator. The third input pulse
initiates a second output pulse.

      The end result is a pulse generator with the following
attri...