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Semiconductor Die Encapsulant With Intrinsic Release Layer

IP.com Disclosure Number: IPCOM000121038D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 92K

Publishing Venue

IBM

Related People

Christiansen, RA: AUTHOR [+2]

Abstract

Electronic packaging of silicon semiconductor die directly mounted onto and wirebonded to circuit boards, then protected by a dispensed epoxy encapsulation has been in practice a number of years for small electronic assemblies where physical size and/or cost factors are important. To eliminate encapsulated wire breakage, encapsulant materials of high glass transition (Tg) and low thermal expansion coefficients are utilized. These materials adhere tenaciously to the circuit board assembly surfaces, including pads used for wirebonding from the board to the die. This renders rework of failed semiconductor die by removal of this encapsulant to be very difficult, often uneconomic, and frequently with high assembly scrap rates.

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Semiconductor Die Encapsulant With Intrinsic Release Layer

      Electronic packaging of silicon semiconductor die
directly mounted onto and wirebonded to circuit boards, then
protected by a dispensed epoxy encapsulation has been in practice a
number of years for small electronic assemblies where physical size
and/or cost factors are important.  To eliminate encapsulated wire
breakage, encapsulant materials of high glass transition (Tg) and low
thermal expansion coefficients are utilized.  These materials adhere
tenaciously to the circuit board assembly surfaces, including pads
used for wirebonding from the board to the die.  This renders rework
of failed semiconductor die by removal of this encapsulant to be very
difficult, often uneconomic, and frequently with high assembly scrap
rates. The difficulty of (and expense) of rework and high scrap rates
is an inhibiting factor to the utilization of this directly attached
("chip-on- board") type of electronic assembly for assemblies of
increasing chip counts.

      This article describes a method of building into the board
assembly a separation layer material applied to the circuit after die
attachment and wirebonding interconnection, but before the
encapsulation process, for the purpose of facilitation of rework, if
required.

      The function of this release layer is to provide a selectively
soluble interface between the circuit board and the epoxy
encapsulation material which meets the criteria of maintaining
integrity of the environmental protection for the semiconductor,
while simultaneously providing a method of removing a failed
semiconductor chip, wirebonds and epoxy glob-top without da...