Browse Prior Art Database

Deep-Submicron Tungsten-Polysilicon Inverse-T Gate

IP.com Disclosure Number: IPCOM000121063D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 4 page(s) / 112K

Publishing Venue

IBM

Related People

Gambino, JP: AUTHOR [+4]

Abstract

In recent years, several MOSFET structures have been proposed, such as the double diffused drain (DDD), the lightly doped drain (LDD), and the inverse-T LDD (ITLDD), to reduce hot electron effects. Among these structures, ITLDD gate devices have the best transconductance, especially when the effective gate length is less than 0.3 mm. This is because in the ITLDD structure both the n-LDD and n+ source/drain implants are aligned under the edge of the gate thus, reducing the channel series resistance [1]. However, the existing ITLDD processes are difficult to fabricate reproducibly. For example, the original structure [2] uses a timed etch in order to leave a thin polysilicon layer. Another version uses a thin oxide in between two polysilicon layers as an etch stop, with sidewall polysilicon as a link [3].

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Deep-Submicron Tungsten-Polysilicon Inverse-T Gate

      In recent years, several MOSFET structures have been
proposed, such as the double diffused drain (DDD), the lightly doped
drain (LDD), and the inverse-T LDD (ITLDD), to reduce hot electron
effects.  Among these structures, ITLDD gate devices have the best
transconductance, especially when the effective gate length is less
than 0.3 mm.  This is because in the ITLDD structure both the n-LDD
and n+ source/drain implants are aligned under the edge of the gate
thus, reducing the channel series resistance [1].  However, the
existing ITLDD processes are difficult to fabricate reproducibly.
For example, the original structure [2] uses a timed etch in order to
leave a thin polysilicon layer. Another version uses a thin oxide in
between two polysilicon layers as an etch stop, with sidewall
polysilicon as a link [3].

      In this article, we propose a tungsten/polysilicon gate ITLDD
process.  Fabrication steps for an NMOS transistor are outlined
below:
1.   A gate oxide is grown on an appropriate substrate, and thin
polysilicon (500 to 1000 Angstroms) is deposited.
2.   A three-layer dielectric stack is formed by coating with
polyimide (5000 Angstroms), depositing PECVD Si3N4 (2000 Angstroms),
and coating with polyimide (5000 Angstroms) (Fig. 1).
3.   An opening is etched in the dielectric stack where the gate will
be fabricated, using lithography and RIE (O2 RIE for polyimide, CF4
RIE for Si3N4).
4.   SiO2 spacers are formed on the...