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High Density Sram Structure With a New Three-Dimensional, High-Performance, High-Packing Density, Planar Inverter Design

IP.com Disclosure Number: IPCOM000121065D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 4 page(s) / 152K

Publishing Venue

IBM

Related People

Gambino, JP: AUTHOR [+5]

Abstract

A stacked polysilicon PMOS load technique has been recently used to achieve very high density SRAMs [1]. Such devices can have low leakage currents and require no extra space and are, therefore, suitable for memory cells with low voltage operation margin. However, problems with this SRAM structure include: (1) severe topography, (2) tendency to form polysilicon residual railings, (3) high gate interconnection resistance and (4) formation of unwanted parasitic capacitances between polysilicon layers.

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High Density Sram Structure With a New Three-Dimensional, High-Performance,
High-Packing Density, Planar Inverter Design

      A stacked polysilicon PMOS load technique has been
recently used to achieve very high density SRAMs [1].  Such devices
can have low leakage currents and require no extra space and are,
therefore, suitable for memory cells with low voltage operation
margin.  However, problems with this SRAM structure include:  (1)
severe topography, (2) tendency to form polysilicon residual
railings, (3) high gate interconnection resistance and (4) formation
of unwanted parasitic capacitances between polysilicon layers.

      An unique planar, shared-gate inverter design is proposed here
for high-density SRAM fabrication.  The LDD-type NMOS device can be
fabricated by using any process where the source-drains are
planarized to the gate, for example, a FET.  The gate length ratio of
PMOS to NMOS can be adjusted to an optimum value to achieve best
switching performance.  The source/drain doping of the polysilicon
PMOS transistors is done through a self-aligned scheme, and no extra
implant mask is needed.  Finally, this three-dimensional (3-D) MOSFET
inverter can be integrated with any conventional vertical npn bipolar
device.

      A possible process sequence for fabricating the SRAM is as
follows:
      1.   Grow 2.5 um of p- epi on a p+ wafer.
      2.   Deposit an in-situ n-type doped CVD polysilicon layer,
about 1200 Ao thick at a concentration about 1E20/cm3 .  This layer
is the diffusion source and contact for the NMOS source/ drain.
      3.   Grow thermal oxide 500 Ao and then deposit a layer of CVD
oxide/nitride about 1200 Ao (Fig. 1).
      4.   Form trench isolation; deep and shallow trench, if
necessary.
      5.   Pattern and RIE etch vias in CVD oxide/nitride and thermal
oxide insulators.  Fill vias with a barrier metal and a thick
refractory metal (or silicide) and chem-mech back to the nitride
surface (Fig. 2).
      6.   A 2500 Ao thickness of p++ poly is deposited and capped
with a thin layer of CVD oxide/nitride. This is the diffusion source
and contact for the PMOS source/drain.
      7.   Pattern with resist and RIE etch the cap layer and p+
polysilicon layer to define the gate area. Etch stop at the nitride
layer (Fig. 3).
      8.   A layer of CVD TEOS with proper thickness is deposited and
etched down to the n+ polysilicon surface to form sidewall.  The
spacer dimension determin...