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Browse Prior Art Database

Fast, Small First-In, First-Out Buffer

IP.com Disclosure Number: IPCOM000121071D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 5 page(s) / 141K

Publishing Venue

IBM

Related People

Nathanson, BJ: AUTHOR

Abstract

The circuit described is a first-in, first-out (FIFO) buffer suitable for applications that require high speed and small memory capacity.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Fast, Small First-In, First-Out Buffer

      The circuit described is a first-in, first-out (FIFO)
buffer suitable for applications that require high speed and small
memory capacity.

      An example of the FIFO datapath is shown in Fig. 1; this
datapath is embodied in Am29520 integrated circuit manufactured by
Advanced Micro Devices.  Control circuitry disclosed here permits use
of the datapath as a FIFO.

      The datapath is a pair of byte-wide shift registers, any of
whose locations can be read through a multiplexer (mux).  The two
shift registers may be clocked and fed data individually, as the
figure shows.

      A bare shift-register/mux combination makes a poor FIFO. After
new data is loaded into the shift register, the mux no longer views
the oldest input, and so the output is temporarily incorrect while
the mux select is moved forward.

      To provide stable output, a double-buffering technique is used:
data is loaded into whichever shift register the mux is not viewing.
A state machine is used to sequence through the trail of data, which
may wind a complicated path through the registers.

      Denote the shift registers as A and B.  For simplicity we
consider that each has only two cells.  Within each register, denote
the cell nearer the input as 0.

      The state machine initializes with the mux viewing A0, with a
FIFO-empty indication being given, and with inputs being loaded into
shift register B.  Alternatively, in this special case, the mux can
read from the same shift register that data is being loaded into.
After an input is loaded into B, the empty indication is removed, the
mux views B0, and further inputs are directed to A.  Here the
possibilities fork:
1.   the data may be read before new data is written,
2.   new data may be written before the data is read, or
3.   new data may be written simultaneously as the data is read.

      In case 1, the state machine returns to the initial, empty
state, except in a "flipped" configuration.  Data now is loaded into
B and the mux views A.  In cases 2 and 3, the mux continues to
view B0 and data continues to b...