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Source-drain Formation for Cmos Transistors Formed by Outdiffusion From Polysilicon

IP.com Disclosure Number: IPCOM000121076D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 4 page(s) / 131K

Publishing Venue

IBM

Related People

Subbanna, S: AUTHOR [+2]

Abstract

Disclosed is an integrated process to fabricate n-channel and p-channel field-effect transistors (FETs) with diffused source-drain junctions formed by outdiffusion from polysilicon. In this way, very shallow junctions can be obtained, as required for short-channel FETs. Because of channeling and annealing required to remove ion-implant damage, it is difficult to obtain such shallow ion-implanted junctions, especially for the p-channel FET. The process described below is for FETs without LDD, but it can be extended to include LDD devices.

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Source-drain Formation for Cmos Transistors Formed by Outdiffusion
From Polysilicon

      Disclosed is an integrated process to fabricate n-channel
and p-channel field-effect transistors (FETs) with diffused
source-drain junctions formed by outdiffusion from polysilicon.  In
this way, very shallow junctions can be obtained, as required for
short-channel FETs.  Because of channeling and annealing required to
remove ion-implant damage, it is difficult to obtain such shallow
ion-implanted junctions, especially for the p-channel FET.  The
process described below is for FETs without LDD, but it can be
extended to include LDD devices.

      In prior art, ion-implanted polysilicon has been used to obtain
diffused source-drain junctions [*].  However, a thick (200 nm) layer
of polysilicon is used, and over-oxidation is necessary, making it
difficult to obtain junction depths less than 150 nm.

      After formation of n- and p-wells, oxide isolation, and
VT-adjust, channel-stop and guard-ring implants, the gate oxide is
grown, and gate poly is deposited (Fig. A).  The next masking step is
used to define the p-FET area and leave the poly over the n-FET area.
The poly is etched down to the silicon.  The exposed gate oxide is
then wet etched (Fig. B), and a thin (10-20 nm) P++ (>1E21 cm-3
boron-doped) polysilicon layer is deposited, followed by a thin (20
nm) PECVD oxide.

      The next mask is used to block out the p-FET.  The oxide and
p+layer are then etched off the n-FET area and isolation.  At the end
of this step, the poly over the n-FET area is exposed (Fig. C).

      A similar procedure is done to define the n-FET.  The next mask
is used to blockout the p-FET area and define the n-FET gate.  The
n-FET gate is then formed using RIE, and the remaining oxide on the
source- drain area is wet etched. A thin n++ poly layer (10-20 nm) is
then deposited.  The following mask is used to blockout the n-FE...