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Differential Summing Amplifier for Optical Signal Detection

IP.com Disclosure Number: IPCOM000121081D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 119K

Publishing Venue

IBM

Related People

Dreps, DM: AUTHOR [+2]

Abstract

The following disclosed circuit provides a means of detecting the presence of small optical signals in an environment where the electrical input signals are so small that they rival the peak amplitudes of inherent transistor noise. The differential circuit arrangement disclosed has excellent noise rejection, and because of its unique placement in the linear section of an optical receiver (see block diagram), the circuit adds no additional noise to the receiver front end. This is important in the design of a sensitive optical receiver in the additional noise sources on the front end of a receiver prevent operation at a low bit error rate for small signal inputs.

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Differential Summing Amplifier for Optical Signal Detection

      The following disclosed circuit provides a means of
detecting the presence of small optical signals in an environment
where the electrical input signals are so small that they rival the
peak amplitudes of inherent transistor noise.  The differential
circuit arrangement disclosed has excellent noise rejection, and
because of its unique placement in the linear section of an optical
receiver (see block diagram), the circuit adds no additional noise to
the receiver front end.  This is important in the design of a
sensitive optical receiver in the additional noise sources on the
front end of a receiver prevent operation at a low bit error rate for
small signal inputs.  In operation, the circuit supplies the computer
system with an optical detection scheme that discriminates noise from
a low level optical signal and indicates to the system if the optical
input is missing.  The output supplied from the disclosed circuitry
looks to the system interface as a TTL compatible voltage swing.

      The loss of light circuit, shown in Fig. 1, consists of a
summing amplifier, integrator with hysteresis, and output stage.  An
"on- module" surface mount compensation/delay capacitor is used.  The
remaining blocks are the receiver functions.

      The summing amplifier is shown in more detail in Fig. 2; nodes
1 and 2 are summing points.  Voffset is applied across q1 and a2.
The offset voltage is determined by modeling the effective amplifier
gain as  a function of received light level.  After this relationship
is established the offset voltage is integrated in the chip to
achieve the desired trigger level.
      Voffset = VBE1 + (I1*3R1)-(I2*3R1)-VBE2
      The DC offset of nodes 1 and 2 is approximately:
(Voffset/3R1)*R2.

      If the differential swing coming into IN and NIN is greater
than (Voffset/3), then a phase difference occurs at nodes 1 and 2.
The differential amplifier amplifies the phase difference and outputs
pulses (light from the transmitter received, normal operation).

      Note:  The differential swing...