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CMOS Device Using Low Temperature Gate Process

IP.com Disclosure Number: IPCOM000121087D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 81K

Publishing Venue

IBM

Related People

Aitken, JM: AUTHOR [+2]

Abstract

In conventional CMOS fabrication, the gate material is exposed to a number of high temperature processes. The most severe processes are generally the sidewall oxidation following gate RIE (700-900~C) and the source/drain drive-in (900~C). Hence, the gate material must be stable during these heat treatments and must not affect the underlying gate oxide or silicon. At the same time, to achieve surface channel devices (as opposed to buried channel devices), the work function difference between the gate material and the substrate must be low (i.e., the threshold voltage must be 0.6 V or less). Because of these requirements, the choices for gate fabrication are limited to refractory materials, such as polysilicon (n+ for nFETs and p+ for pFETs), MoSi2, WSi2, Mo and W.

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CMOS Device Using Low Temperature Gate Process

      In conventional CMOS fabrication, the gate material is
exposed to a number of high temperature processes.  The most severe
processes are generally the sidewall oxidation following gate RIE
(700-900~C) and the source/drain drive-in (900~C).  Hence, the gate
material must be stable during these heat treatments and must not
affect the underlying gate oxide or silicon.  At the same time, to
achieve surface channel devices (as opposed to buried channel
devices), the work function difference between the gate material and
the substrate must be low (i.e., the threshold voltage must be 0.6 V
or less). Because of these requirements, the choices for gate
fabrication are limited to refractory materials, such as polysilicon
(n+ for nFETs and p+ for pFETs), MoSi2, WSi2, Mo and W.  Mo and W
and their silicides can form volatile oxides during oxidation,
resulting in delamination [1]. Therefore, polysilicon is the most
widely used gate material in the manufacture of CMOS devices.

      All of the problems described above could be avoided with a
process where the gates are fabricated after the source/drains.  One
way to do this is to use a process similar to that used for double
polysilicon bipolar transistors [2].  The process uses diffusion from
polysilicon to form the source/drain junctions.  Then, the
source/drain polysilicon is etched to form a gate opening, sidewalls
are fabricated, the gate oxide is grown, and finall...