Browse Prior Art Database

Addressed Writeable And Associative Readable Memory

IP.com Disclosure Number: IPCOM000121091D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 4 page(s) / 137K

Publishing Venue

IBM

Related People

Heddes, M: AUTHOR

Abstract

Described is an addressed writable and serial associative readable contents-addressed memory (CAM) which needs fewer transistors as compared to conventional CAMs, and which has a new multiple match resolver (MMR) circuit, in which address decoder, address encoder and priority encoder are combined into one circuit. The CAM with MMR can be used for an efficient implementation of a large number of timers.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Addressed Writeable And Associative Readable Memory

      Described is an addressed writable and serial associative
readable contents-addressed memory (CAM) which needs fewer
transistors as compared to conventional CAMs, and which has a new
multiple match resolver (MMR) circuit, in which address decoder,
address encoder and priority encoder are combined into one circuit.
The CAM with MMR can be used for an efficient implementation of a
large number of timers.

      The CAM bit cell is based on a write-only memory (WROM) bit
cell, as shown in Fig. 1.  Addressed writing is done by making the W
lines of the addressed word low (the  W  line of all bit cells in a
word are connected together).  D(0) and D(1) are then used to set or
reset the flipflop Q1-Q2. The figure shows an nMOS implementation,
but it can be changed to CMOS by using transistors instead of
resistors.

      Associative reading operates on a bit-by-bit base, which
requires additional circuitry.  A global circuit, shared by all
words, is needed to control the datalines D(0) and D(1) of all bit
cells.  Further, for each  word a match-flip-flop (MFF), to remember
the result of the compare, is required.  The MFF is initialized
(e.g., cleared) and the W line, precharged high, is connected to the
set input of the MFF.  All bits in a word are separately compared
with their datalines.  The datalines of the first bit to be compared
are given their value and the datalines of the other bits are kept
inactive.  If a mismatch occurs, the W line will become  "O", which
sets the MFF.  Then the second bit is compared with its datalines,
etc.  At the end of the process, the MFF will only be cleared if all
bits in the word matched their datalines.  Instead of a serial
compare, all bits can be compared simultaneously if two transistors
are added to the circuit in an obvious way.

      In addition to the CAM array, a priority encoder, an address
encoder and an address decoder are required.  The number of
transistors required to implement these circuits can be decreased by
combining the three circuits into one Multiple Match Resolver (MMR)
circuit.  An example is shown in Fig. 2.  This MMR modu...