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Hardware Cycle Simulation Coverage Measurement Tool

IP.com Disclosure Number: IPCOM000121099D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 81K

Publishing Venue

IBM

Related People

Caillet, B: AUTHOR [+2]

Abstract

The (Compiled) Enhanced Functional Simulator ((C)EFS) is used to verify the Independent-Technology logic described in Basic Design Language for Cycle Simulation (BDL/CS).

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Hardware Cycle Simulation Coverage Measurement Tool

      The (Compiled) Enhanced Functional Simulator ((C)EFS) is
used to verify the Independent-Technology logic described in Basic
Design Language for Cycle Simulation (BDL/CS).

      Such a logic is based on assignment statements and decision
blocks which can be analyzed in two ways:

      - the DATA FLOW analysis checks how the logic Boolean values
are propagated.  It verifies that latches and buses have correct
values at specific times ("expected value" notion);

      - the CONTROL FLOW analysis checks the sequences of switches
and decision elements ("Paths") that lead to a logic state change.
It verifies whether or not they have been activated during the
simulation ("exercised path" notion).

      This article describes a program which quantifies a BDL/CS
logic CONTROL FLOW activation during the simulation phase and so
permits validating the test case coverage.

      The TRACEDIT Report Analysis Program (TRAP) is based on a CEFS
standard output (TRACEDIT report) which gives information at each
simulation cycle on exercised/unexercised decision elements.

      It is built around 5 main menus whose flow is summarized in the
figure.

      The first one (1) calls the programs that build a Path File
containing the list of all the logic decision Paths and some
information necessary for the activation measurement.

      The second one (2) calls the CEFS simulation results collection...