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Bicmos Tristate 3 V Lvttl 5 V Compatible Off-Chip Driver

IP.com Disclosure Number: IPCOM000121127D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 126K

Publishing Venue

IBM

Related People

Boudon, G: AUTHOR [+2]

Abstract

To improve the performance of a CMOS circuit in the case of a high loading, the bipolar has been associated with the CMOS structure. The traditional BiCMOS logic circuits used in internal cells of an integrated circuit are very efficient to drive high load capacitances without DC power dissipation, but in the case of a DC current, the output never goes below a Vbe = 0.8 V which is not compatible with TTL levels.

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Bicmos Tristate 3 V Lvttl 5 V Compatible Off-Chip Driver

      To improve the performance of a CMOS circuit in the case
of a high loading, the bipolar has been associated with the CMOS
structure.  The traditional BiCMOS logic circuits used in internal
cells of an integrated circuit are very efficient to drive high load
capacitances without DC power dissipation, but in the case of a DC
current, the output never goes below a Vbe = 0.8 V which is not
compatible with TTL levels.

      In the previous art, different methods are used to antisaturate
the bottom NPN transistor, mainly the use of Schottky diodes between
emitter and collector, antisaturation devices using diodes, or the
bottom NPN device is simply replaced by a NFET device in order that
the down level be lower than 0.5 V to be compatible with TTL levels.

      This article describes a BiCMOS tristate off-chip driver
compatible with TTL levels with 3.3 V-3.6 V and 5.0 V power supply
and without Schottky diode for antisaturation. Its input DATA is A0
and its OUTPUT is controlled by an Enable signal HZ. The Enable
signal HZ must be at 0 to have the DATA Out equal to the DATA
In. In tristate mode (high impedance, HZ = 1), the output dotted to
other driver outputs can receive a high voltage signal (5.5 V).

      The antisaturation of the bottom NPN is achieved with
transistors N6, N7 and T4. The voltage defined across N7 is equal to
the Vce of T2 which allows keeping the transistor out of saturation
with a Vce in the 0.2 - 0.4 V range.  At down level the output
goes down to approximately 0.3 V while at up level transistors N3 and
N4 are off to prevent a DC current through N6, N7 and N8.

      The limitation of the current peak and the dI/dt in the ground
and Vdd buses during the up- and down-going transitions are achieved,
respectively, with transistors N11-N12 and N10.  At the beginning of
the rising transition, N11 is turned on, N12 being always on with 2.2
V on its gate, and part of the current delivered by P0, P1, P2 and
P3 is derived in N11 and N12, thus limiting the current in the base
of T1 and, therefore, the collector current.  As the output rises,
N11 becomes less and less efficient, thus not slowing down the end of
the transition and the same thing with N10 for T2 for the falling
transition.  This technique with emitter base shortage has permitted
limiting the dI/dt while keeping a high performance circuit.  N10,
N11 and N12 also have a p...