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Browse Prior Art Database

BiCMOS Selector

IP.com Disclosure Number: IPCOM000121129D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 118K

Publishing Venue

IBM

Related People

Moitie, R: AUTHOR [+2]

Abstract

A new circuit design of the selector function in BiCMOS technology is disclosed below.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

BiCMOS Selector

      A new circuit design of the selector function in BiCMOS
technology is disclosed below.

      The design of the electrical schematic of the selector circuit
is shown in the figure.

      The selector circuit provides the capability to select one data
out of four data in: A0, A1, A2 and A3. The right combinations of the
control lines S0 / S0C and S1 / S1C pick the required data in.  The
circuit assumes the external generation of S0C from S0, S0C = S0--
and S1C from S1, S1C = S1--, respectively.  The complementary value
of the selected lines is required to command the full pass-gates of
the four inputs.  It has  two stages:

      - the first stage ensures the selection of the right data in,
through the proper combination of the input transfer gates. TP01 /
TN02 and TN01 / TP02 select, respectively, A0 or A1; TP04 / TN03 and
TP03 / TN04 select, respectively, A2 or A3, both selections are made
with S0 / S0C.  The next level of selection is realized through TNG1
/ TPG1 for the first couple A0 / A1 and through TNG2 / TPG2 for
the second couple A2 / A3. This time both selections are made with S1
/ S1C.  This first stage, aimed to accomplish the selection, is built
only from FET transistors for optimal density, since the load
capacitances at the internal nodes are quite low.

      - the second stage provides the driving capability of the
overall circuit.  The output push-pull driver is made from NPN
bipolar transistors TBIP1 and TBIP2 drive the high-level output, and
TBIP3 drives the low-level output. Transistors TD1 / TD2 and TD5 /
TD6 command the low-level conditions from both pairs of entries.  TD5
/ TD6 are on when node X1 and S1C are at 0 level.  The transistor
TBIP3 is passing to force a 0 on the output line.  Similarly, TD1 /
TD2 turn on TBIP3 depending on the conditions of the other inputs A0,
A1 and select S0 / S0C. TD7 / TD8 for one side, and TD3 /
TD4 for the other side, duplicate the same function.  However, the
command of their gates are reversed to improve balance and
performance of the 0 level detection.

      Transistors TR1 / TR2, resistors TR1 / TR2 and diode TBIP4
prevent that the reverse base-emitter voltage, Vbe, of transistors
TBIP1 / TBIP2 goes hig...