Browse Prior Art Database

Method of Communicating Between a Microprocessor And a Microcontroller

IP.com Disclosure Number: IPCOM000121147D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 5 page(s) / 222K

Publishing Venue

IBM

Related People

Rowe Jr, JT: AUTHOR

Abstract

When a system has a microprocessor and a microcontroller, some method of communication between the two chips must be set up. If the chips are operating from different clock sources or if the chips execute instructions at different speeds, the communication method must synchronize the two chips. The following method can be used to synchronize a processor and controller with a minimum of hardware.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 37% of the total text.

Method of Communicating Between a Microprocessor And a Microcontroller

      When a system has a microprocessor and a microcontroller,
some method of communication between the two chips must be set up.
If the chips are operating from different clock sources or if the
chips execute instructions at different speeds, the communication
method must synchronize the two chips.  The following method can be
used to synchronize a processor and controller with a minimum of
hardware.

      This synchronization method uses a combination of external
hardware and microcontroller software to extend a bus cycle of the
microprocessor.  An "extend" signal generated by the controller is
initialized to the inactive state by the controller.  When the
processor reads or writes to the controller, the address "chip
select" signal is routed through logic to immediately extend the
processor's bus cycle.  The "chip select" signal is also used to
cause an interrupt in the controller.  The "extend" signal is changed
to the logic level necessary to end the bus cycle extension when the
microcode in the controller has completed the task (read or write)
the processor desired.  Refer to Fig. 1 for a representative
schematic, and refer to Fig. 2 for a representative timing diagram.
For sample purposes, these diagrams assume an 80188 as the processor
and an 8051 as the controller.
Basic Synchronization Operation

      Read Operation:  Referring to the "read" diagram in Fig. 2, the
following sequence of events would take place (letters refer to
operations in the processor and numbers refer to operations in the
controller):
   O) Assuming the controller wanted to tell the processor something,
the controller would lower pin PY.Y to cause an interrupt on the
processor.  (This step is optional; the operation could start at
steps A and 1 if the controller knew what the processor wanted to
read.)
   A & 1) The processor executes a read operation with the "-CS",
"-RD", and "DEN" signals being generated in hardware from the
processor.  The "-CS" signal causes the OR gate to change states,
with "SRDY" now being inactive at the low level.  "SRDY" at a low
level will extend the processor's read cycle until it is raised to a
high level by the controller signal "-Extend".

      The negative-going edge of "-CS" will also cause the highest
level interrupt in the controller.
   2) After the controller has responded to the interrupt and started
executing the interrupt routine, the controller will read the state
of the "-RD" line on pin PX.X.  The interrupt routine will read a low
level and proceed to the "Read" routine.
   3) Pin PY.Y would be raised to prevent an additional interrupt in
the processor.
   4) The controller will place the data to be sent to the processor
on its data lines (D7-D0).
   5 & B) The controller will raise "-Extend".  This will cause the
"SRDY" signal into the processor to go high.  The processor will now
complete the "Read" o...