Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Balance Capacitor to Reduce Resonance Noise

IP.com Disclosure Number: IPCOM000121157D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 1 page(s) / 30K

Publishing Venue

IBM

Related People

Smith, LD: AUTHOR

Abstract

A capacitor is added from logic ground to chip substrate to provide coupling equal to that of high voltage source VDD to chip substrate. Noise coupled to the chip substrate from ground and from VDD becomes equal and opposite. This significantly reduces resonance noise coupled to the chip substrate each time a clock switches.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Balance Capacitor to Reduce Resonance Noise

      A capacitor is added from logic ground to chip substrate to
provide coupling equal to that of high voltage source VDD to chip
substrate.  Noise coupled to the chip substrate from ground and from
VDD becomes equal and opposite.   This significantly reduces
resonance noise coupled to the chip substrate each time a clock
switches.

      Referring to the figure, high supply VDD and ground Gnd are
connected as usual to logic circuits through package inductances L1
and L2.  Ohmic substrate contacts are replaced by capacitor C3 which
is sized to make coupling to the substrate S from both power supplies
equal.  Circuit A, which carries no power supply current and connects
from substrate S through package inductance L3 back to Gnd is added
to conventional circuitry.  Out of phase noise of equal amplitude
coupled into the substrate from the two supplies is thereby nulled
out.

      Disclosed anonymously.