Browse Prior Art Database

Test Method for Gate Array

IP.com Disclosure Number: IPCOM000121212D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 61K

Publishing Venue

IBM

Related People

Taniguchi, M: AUTHOR

Abstract

Disclosed is a test method for gate array to test all basic cells on the chip before making a personalized circuit on it.

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This is the abbreviated version, containing approximately 80% of the total text.

Test Method for Gate Array

      Disclosed is a test method for gate array to test all
basic cells on the chip before making a personalized circuit on it.

      In gate array, as so many transistors are integrated in a chip,
it is getting hard to detect errors in it.  The best way to test all
NMOS and PMOS transistors is to make inverters and compose a ring
oscillator using those inverters.  The frequency of ring oscillator
is determined by the delay time of each inverter.  So if there is any
defect device in the ring oscillator, the frequency of it will be
different from the expected one, and in the worse case, it will not
oscillate. To do this test method, the back end process takes two
steps in 1st metal process.  First, ring oscillators are composed
using 1st metal.  Second, after measuring the frequency of the ring
oscillators, 1st metal is partially etched to obtain personalized
circuit.

      Fig. 1 shows an example of how to compose the ring oscillator.
In this case, the personalized circuit is 2-way NAND.  First, two
inverters that are serially wired are made.  In Fig. 1, input signal
X is connected to the output of inverter in the left basic cell and Y
is connected to the input of the inverter in right basic cell.  In
this manner, all inverters in the same row can be connected in
serial.  The output of the leftmost inverter of the row is wired to
the input of the most right side inverter of the row through channel
area.
      Fig. 2 sho...