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Browse Prior Art Database

Double Frequency Clock Generator

IP.com Disclosure Number: IPCOM000121221D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 62K

Publishing Venue

IBM

Related People

Nishihara, M: AUTHOR

Abstract

Disclosed is a simple but effective clock generator circuit which can generate double frequency waveform from input reference clock. The circuit does not require sophisticated analog techniques like phase- locked loop (PLL). The circuit can be used in a cascaded manner to get a higher frequency of power of 2.

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This is the abbreviated version, containing approximately 68% of the total text.

Double Frequency Clock Generator

      Disclosed is a simple but effective clock generator
circuit which can generate double frequency waveform from input
reference clock.  The circuit does not require sophisticated analog
techniques like phase- locked loop (PLL). The circuit can be used in
a cascaded manner to get a higher frequency of power of 2.

      Referring to the figures, a reference clock applied to input
pad 10 is divided into two paths.  One path includes VCDLY (Voltage
Controlled Delay) circuit 12 and DTV (Duty to Voltage) conversion
circuit 14, and the other path includes XOR (Exclusive OR) circuit 16
and second DTV conversion circuit 18.  The VCDLY 12 provides a
controlled delay over the original clock waveform.

      The output from VCDLY 12 at node N1 and the input clock at pad
10 are applied to XOR 16.  The output from XOR 16 at node N2 is
a double frequency clock waveform but does not have a good duty
factor.  The duty factor of the generated clock waveform can be
controlled by changing the delay amount of the VCDLY 12.  In order to
generate a control voltage to VCDLY 12, the clock waveforms at nodes
1 and 2 are applied to DTV conversion circuits 14 and 18 which
convert the duty factors of the respective clock waveforms to
corresponding voltages.

      The output voltages from DTV circuits 14 and 18 are compared by
comparator 20.  The output from comparator 20 indicates the
difference between duty factors of the two clock waveform...