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Browse Prior Art Database

Bias Technique for ECL in BiCMOS Technology

IP.com Disclosure Number: IPCOM000121228D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Dhong, SH: AUTHOR [+2]

Abstract

Disclosed in the figure is a new bias technique for ECL (Emitter- Coupled Logic) circuits in BiCMOS technology. The new technique utilizes the MOSFET current source (MCS) and precise BiCMOS bias circuit (M1-M7, Q1-Q4) instead of the conventional bipolar-transistor current source and bias circuit, to minimize the current error, circuit area, and power consumption.

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This is the abbreviated version, containing approximately 59% of the total text.

Bias Technique for ECL in BiCMOS Technology

      Disclosed in the figure is a new bias technique for ECL
(Emitter- Coupled Logic) circuits in BiCMOS technology.  The new
technique utilizes the MOSFET current source (MCS) and precise BiCMOS
bias circuit (M1-M7, Q1-Q4) instead of the conventional
bipolar-transistor current source and bias circuit, to minimize the
current error, circuit area, and power consumption.

      Because MOSFET has zero DC gate current, if M1 and MCS have
equal width/length ratio (=W/L), the reference current IR will be
exactly mirrored to ICS, regardless of how many current sources are
connected to the bias potential VB. Also, the MOSFET current source
is advantageous for the cascoded ECL because the node potential at X
can be lowered very close to VEE without affecting ICS.  This is
achieved by increasing the W/L of MCS and thus minimizing the
drain-source saturation voltage.

      The reference current IR is generated in the negative-feedback
circuit (M1-M5, Q1-Q4) and precisely controlled so that the ECL
output signal at O is always centered at VR, even though the
resistance and transistor characteristics may vary.  Note that the
half circuit of standard ECL with its output and input tied together
(Q1, Q2, RC, 2RS, RT and M2 circuit) is used to monitor the
resistance and VBE variation.  Here, Q1 is equal to QI, Q2 is
identical to QEF, and the size of M2 is half of MCS.  Therefore, if
all parameters are as designed, the output po...