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Browse Prior Art Database

Tagged Inter Processor Communication Bus for Multiprocessor Systems

IP.com Disclosure Number: IPCOM000121240D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 7 page(s) / 251K

Publishing Venue

IBM

Related People

Garcia, A: AUTHOR

Abstract

A low-latency inter processor communication (IPC) bus structure is described that supports multiple processors communicating between each other and other devices on a shared bus. It utilizes a tagging scheme to uniquely identify multiple outstanding requests and supports simultaneous processor read requests and memory replies during the same bus cycle. Introduction

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This is the abbreviated version, containing approximately 29% of the total text.

Tagged Inter Processor Communication Bus for Multiprocessor Systems

      A low-latency inter processor communication (IPC) bus
structure is described that supports multiple processors
communicating between each other and other devices on a shared bus.
It utilizes a tagging scheme to uniquely identify multiple
outstanding requests and supports simultaneous processor read
requests and memory replies during the same bus cycle.
Introduction

      One potential bottleneck in any bus-oriented multiprocessor
system is the bandwidth required between processors and the shared
memory system.  The approach usually taken in designing the high
bandwidth shared bus in a multiprocessor system is to provide wide
data paths (e.g., 64 to 128 bits wide) and to use conventional
uniprocessor bus protocols.  That is, processors arbitrate for the
bus and then keep it for the entire duration of the memory read or
write cycle.  During this time, no other processor may communicate
with another device on the shared bus.  This results in a limited
utilization of the bus, which accounts for one of the bottlenecks in
bus-oriented multiprocessor systems.

      One way to minimize the time taken to perform read/write cycles
on a multiprocessor shared bus is to decouple devices from the bus
while the memory device is performing the actual read/write cycle.
That is, processors simply need use the bus to transfer a read or
write request, which memory devices consume.  For the case of a write
request, the memory device acknowledges the processor upon accepting
the request and then proceeds to actually perform the memory write
cycle. However, during this time, the shared bus can be used by
processors to perform other shared memory requests. Similarly, for a
read request, the memory device acknowledges the processor upon
accepting the request, performs the memory read cycle, and then
requests the bus to return the actual data.  As before, the bus is
free during the memory read cycle.

      Thus, assuming that the shared memory system consists of
independently controlled banks of memory, several processor
read/write requests can be serviced simultaneously.  This
significantly improves the bandwidth capability of the shared bus
since, in practice, different processors will access distinct banks
in the memory system. To accomplish this, processors need to "tag"
memory read requests so that memory replies can be uniquely
identified by the requesting processors.  Each processor needs at
least one unique tag but can use more to support several outstanding
read requests.
IPC Bus

      The IPC bus is a high-performance bus tailored to supporting
multiple processors.  It is designed to maximize throughput for
block- mode transfers, such as DMA transfers between disk controllers
and memory, while minimizing average latency on single cycle shared
memory references by processors.  Furthermore, in order to minimize
system complexity, and hence cost, a const...