Browse Prior Art Database

Method of Address Fault Detection in Embedded Memory

IP.com Disclosure Number: IPCOM000121249D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 78K

Publishing Venue

IBM

Related People

Iadanza, JA: AUTHOR

Abstract

An addressing fault detection architecture is shown for use within a logic chip containing both error detection and correction logic and embedded storage arrays.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method of Address Fault Detection in Embedded Memory

      An addressing fault detection architecture is shown for
use within a logic chip containing both error detection and
correction logic and embedded storage arrays.

      Address fault detection is provided by splitting a single array
into two physical arrays, each of which has a dependency on the other
for storage of error correction code (ECC) information. Address fault
detection is thereby generated as a byproduct of standard ECC
checking of stored data within the arrays. This architecture is most
effective when used with multiport arrays where many single port
address faults would be undetectable using an ECC system which does
not incorporate addressing information within the ECC word. The
architecture shown for address fault detection combines segmentation
of a single array containing system data and error
detection/correction data generated by the system into two distinct
arrays, both of which contain a portion of the system data, and a
non-corresponding portion of the ECC code.

      An N bit array, containing X data bits, and Y data ECC bits is
broken into two arrays, i.e., ARRAY1 and ARRAY2, each with X/2 data
bits and Z ECC bits, where Z may or may not equal Y/2, depending upon
the type of ECC implementation. DATA1 and DATA2 refer to the two
segments of X/2 data bits, and ECC1 and ECC2 refer to the two ECC
segments. Each array is a self-contained unit providing its own
dedicated address decode and control; however, both new arrays
perform as a single logical array with shared address generation and
control logic peripheral to the array.

      Referring to the architecture shown in the figure, whe...