Browse Prior Art Database

Low Profile, Pseudo Wafer, Multi-chip Package

IP.com Disclosure Number: IPCOM000121252D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 112K

Publishing Venue

IBM

Related People

Beilstein Jr, KE: AUTHOR [+4]

Abstract

A method is shown for connecting tested chips into a pseudo wafer configuration that provides 1) a chip carrier, 2) a built-in heat sink potential, and 3) photolithographic wiring plane(s) to interconnect chips and provide connection to sockets, cards, or wires leading away from the pseudo wafer.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 51% of the total text.

Low Profile, Pseudo Wafer, Multi-chip Package

      A method is shown for connecting tested chips into a
pseudo wafer configuration that provides 1) a chip carrier, 2) a
built-in heat sink potential, and 3) photolithographic wiring
plane(s) to interconnect chips and provide connection to sockets,
cards, or wires leading away from the pseudo wafer.

      Referring to Fig. 1, chips are placed on the pseudo wafer so as
to accommodate via locations and interconnect wiring. In the case of
DRAMs, it may be necessary to route wiring around active arrays to
minimize coupling and capacitive loading.

      Assembly of the pseudo wafer begins with a metallic sheet
selected for rigidity and thermal conductivity (Fig. 2). The back
side of the sheet may have an appropriate heat sink configuration if
required.  The top side of the sheet is made highly planar and coated
with an adhesive like that used on sticky tape to attach the lead
frame in A-wire packaging. The adhesive thickness is minimized to
enhance heat dissipation and to maintain surface planarity. A
modified chip place ment tool is used to align and position chips
circuit side up on the sticky surface. Also, pseudo wafer wiring
density is a function of chip placement accuracy.

      Once chips are positioned and firmly stuck to the metallic
backing, a ring around the chips is temporarily attached to the back
plate. The ring encloses the region of the chip array and provides
the edge molding surface for casting material to embed the chips. The
ring contains holes/tubes appropriate for injecting a casting
material and is coated with TEFLON* or other material to prevent
adhesion of the casting material to the ring. Several stops are
attached to the metallic back around the periphery for mechanical
lapping. The thickness of the ring and stops is chosen to be the sum
of the nominal thickness of the chips + sticky layer - 1/2 of the
final insulator thickness. To provide a top for molding, a highly
planar plate (not shown) is temporarily placed on top of the pseudo
wafer assembly and pressure is applied to prevent casting material
from coating the surface of the chips. Once the casting material is
set, the top plate is removed. The array of chips is now a pseudo
wafer and can be processed as such.

      The first step for processing the pseudo wafer is to deposit a
polyimide layer. The vias are opened over the existing chip vi...