Browse Prior Art Database

DMA Controller

IP.com Disclosure Number: IPCOM000121262D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 4 page(s) / 151K

Publishing Venue

IBM

Related People

Palmer, MJ: AUTHOR

Abstract

Disclosed is a Direct Memory Access (DMA) controller which features the use of two counters per channel to allow unbounded transfer length. The problem solved is that in high performance disk controllers, data passing between host system and disk drive passes through a data buffer controlled by a DMA controller.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 44% of the total text.

DMA Controller

      Disclosed is a Direct Memory Access (DMA) controller
which features the use of two counters per channel to allow unbounded
transfer length.  The problem solved is that in high performance disk
controllers, data passing between host system and disk drive passes
through a data buffer controlled by a DMA controller.  Advances in
disk controller architecture demand extra function in the DMA
controller to handle, for example,
(a)  large numbers of channels requesting service independently,
(b)  non-stop operation over long transfers (potentially as large as
the disk capacity),
(c)  writing the same data pattern to multiple sectors on a disk as
defined by the SCS1 command 'Write Same', and
(d)  interleaving of data to/from 2 or 4 disk drives, on a
sector-by-sector basis, to form one transfer from/to the host at 2 or
4 times the data rate (striping).

      A controller to cope which these demands provides the following
novel features:
(1)  Use of the data bus for communicating DMA requests to the DMA
controller, rather than using separate signals,
(2)  parity checking of DMA requests, and
(3)  two count values per channel (CNTA and CNTB).
(4)  Interrupts are generated when a DMA operation switches between
CNTA and CNTB allowing microcode to reload the expired count and
achieve continuous operation of arbitary length,
(5)  Interleaving of data from 2 or 4 channels, in or out of the data
buffer, for use with 'striping',
(6)  Wrapping of the DMA address is independent of the channel count,
with the wrap point being adjustable, and
(7)  'write-same' mode which resets the DMA address at the end of
every sector.

      Proposed is a DMA controller, for coordinating data transfer
between DMA slaves and a shared data buffer.  Fig. 1 shows an example
with two DMA slaves, though any number could be present.
      The DMA bus consists of:
           DMA_DATA       The DMA data bus (16 bits), also used for
DMA slaves to signal requests to the DMA Controller.
           ĐGRANT    A line driven by the DMA Controller. While
high, this line indicates that DMA channel requests should be clocked
onto the DMA data bus.  The falling edge indicates that a DMA
transfer is starting, and the acknowledgement of which channel is
active will follow shortly on the DMA data bus.
             CONTROLS       A few other control signals to coordinate
data transfers.

      The DMA controller starts arbitration by raising the
ĐGRANT line.  For each clock cycle that is high, the DMA slaves
drive their requests onto the DMA bus in the following cycle, in a
bit significant fashion (e.g., '8000'x = channel 0, '0001'x = channel
15).  Available channels are assumed to be partitioned between the
DMA slaves so that each bit is driven by exactly one DMA slave:  in
cases where each DMA slave drives several channels (e.g., one slave
uses channels 0 through 7 and another uses 8 throug...