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Multi-level Cache System for MP

IP.com Disclosure Number: IPCOM000121297D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 92K

Publishing Venue

IBM

Related People

Brenza, JG: AUTHOR [+2]

Abstract

This article describes a multi-level cache for a multi-processor (MP) computer configuration. This configuration is illustrated in the figure. Operational characteristics of this configuration are: - Each CPU has both a private L1 and L2 cache. - Two or more CPUs comprise an MP configuration. This involves one or more System Control Elements (SCEs), each with one or more CPUs. - Each L1 cache operates "store-in", whereas each L2 cache operates "store-thru". L1 holds the current data, which is Cast Out (C/O) to L2 before L1 overlays. L2 forwards to L3 any change data lines C/O from L1. - Each SCE has a directory with an entry for each L2 cache line held by each CPU connected to the SCE.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Multi-level Cache System for MP

      This article describes a multi-level cache for a
multi-processor (MP) computer configuration.  This configuration is
illustrated in the figure.  Operational characteristics of this
configuration are:
      -    Each CPU has both a private L1 and L2 cache.
      -    Two or more CPUs comprise an MP configuration. This
involves one or more System Control Elements (SCEs), each with one or
more CPUs.
      -    Each L1 cache operates "store-in", whereas each L2 cache
operates "store-thru".  L1 holds the current data, which is Cast Out
(C/O) to L2 before L1 overlays.  L2 forwards to L3 any change data
lines C/O from L1.
      -    Each SCE has a directory with an entry for each L2 cache
line held by each CPU connected to the SCE.
      -    Each SCE directory entry contains a Read-Only/Exclusive
Bit (RO/E) and a valid/invalid bit for each, corresponding L2 line.
      -    The contents of each L1 cache are a subset of the L2
cache.
      -    L2 lines (e.g., 512 bytes) resident in the private L2
caches are assigned RO/E in the L2 directory.  L1 lines (e.g., 64
bytes) have RO/E assignments corresponding to the source L2 line
assignments.
Operational Description

      This article primarily relates to an improved method for
transferring data between processor private caches in an MP computer
configuration.  Referring to the figure, L1 cache misses cause fetch
requests to L2.  L2 cache misses cause fetch requests to L3.  L3
requests are channeled through the SCE which contains copies of the
L2 directories for its locally attached CPUs.  The SCE will:
      (1)  Issue a fetch request to L3.
      (2)  Issue a search request to its directories.
      (3)  Issue a search request to remote SCE directories.

      For simplicity, the following description is related to two
CPUs; however, the bussing and controls are extendable to (n)
processors.  Assume that CPU #1 experiences an L2 miss and initiated
the above sequence of operations by the SCE.  After searching its
directory, the SCE discovers that the desired data is currently
resident in CPU #2 L2 and L1 caches.  Without canceling the L3
request, the S...