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Browse Prior Art Database

Logic Rich Cell

IP.com Disclosure Number: IPCOM000121298D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 7 page(s) / 255K

Publishing Venue

IBM

Related People

Weinberger, A: AUTHOR

Abstract

The "logic rich cell" concept is applied to gate arrays to take advantage of the fact that a significant number of functional books can be defined with a limited number of LSTs (logic service terminals) that are normally assigned to unit logic books. An LST (logic service terminal) is a cell input/output terminal which is used for a global connection among books. A book is a logic gate or logic function comprised of one or more cells whose components are connected via wiring channels generally assigned for book wiring without interfering with global wiring between books. For example, six LSTs are adequate for functional books, such as XOR, SELECT, AND/OR, OR/AND, etc., in addition to unit logic books, such as OR gates with up to four inputs and with true and complement outputs.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 31% of the total text.

Logic Rich Cell

      The "logic rich cell" concept is applied to gate arrays
to take advantage of the fact that a significant number of functional
books can be defined with a limited number of LSTs (logic service
terminals) that are normally assigned to unit logic books.  An LST
(logic service terminal) is a cell input/output terminal which is
used for a global connection among books.  A book is a logic gate or
logic function comprised of one or more cells whose components are
connected via wiring channels generally assigned for book wiring
without interfering with global wiring between books.  For example,
six LSTs are adequate for functional books, such as XOR, SELECT,
AND/OR, OR/AND, etc., in addition to unit logic books, such as OR
gates with up to four inputs and with true and complement outputs.
Therefore, 1-cell functional books with six or fewer LSTs and 2-cell
functional books with twelve or fewer LSTs can significantly reduce
the number of cells needed to implement larger logic networks.

      Several problems must be overcome to effectively utilize 1-cell
and 2-cell functional books (and some functional books of more than 2
cells).  They are:
     1.   Functional books increase the average LST utilization and,
therefore, the average number of global connections per cell, thereby
making a fully utilized chip less wirable.
      2.   They increase cell component requirements.
      3.   They increase book wiring complexity.
      4.   They generally require added gate levels in series.

      A number of factors are combined to solve these problems:
      1.   More wiring tracks are becoming available to accommodate
both the increased number of cells on a chip as well as imbedded
arrays and other large books.  Additional wiring tracks are in the
form of increased wiring track density as well as added wiring
planes.  The requirement for added wiring tracks is partially
mitigated by the fact that functional books reduce the amount of
global wiring and LSTs for an equivalent amount of chip logic by
shifting a significant portion of global wiring to book wiring.
      2.   Logic circuits that use simple components of few types and
that can be densely packed provide the necessary increased function
for functional books, without necessarily increasing cell area
relative to unit logic per cell.  For example, the GaAs FET logic
comprised of DCFL (Direct Coupled FET Logic) and SFFL (Source
Follower FET Logic) that can be implemented with rows of densely
packed devices (i.e., brick walled devices) meet these criteria.
      3.   Of the additional wiring planes intended for global
wiring, one is assigned to book wiring.  This satisfies the need for
extra book wiring of functional books, while leaving sufficient
global wiring tracks for the reduced global wiring requirements.
      4.   Higher circuit speed and chip logic density increase that
portion of circuit delay...