Browse Prior Art Database

Common Design Footprint for Vendor DRAM SOJ Packages

IP.com Disclosure Number: IPCOM000121300D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 9 page(s) / 167K

Publishing Venue

IBM

Related People

Anzani, MS: AUTHOR [+4]

Abstract

Similarities in the pin assignments and physical footprints of the JEDEC standard packages for the 1Mbit and 4Mbit DRAM offer an opportunity to develop a single raw card design that can accommodate both. This allows memory capacity upgrades during a program with no additional design effort and provides supply flexibility while passing through the transition from 1Mbit to 4MBit (assuming inclusion within the control logic of the full address range at the start of the program).

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Common Design Footprint for Vendor DRAM SOJ Packages

      Similarities in the pin assignments and physical
footprints of the JEDEC standard packages for the 1Mbit and 4Mbit
DRAM offer an opportunity to develop a single raw card design that
can accommodate both.  This allows memory capacity upgrades during a
program with no additional design effort and provides supply
flexibility while passing through the transition from 1Mbit to 4MBit
(assuming inclusion within the control logic of the full address
range at the start of the program).

      This article compares the following DRAMs in both the
Pin-through- Hole (PTH) and Surface Mount Technology (SMT) packages:
      a)   256K x 4  to   1M x 4    (20 PIN PTH, 26/20 SOJ)
      b)     1M x 1  to   4M x 1    (18 PIN PTH, 26/20 SOJ)

      The pin assignments of the packages are first compared for the
cases listed followed by comparisons of the SMT package footprint.
The card design opportunities are then described.
Pin Assignments:
256K x 4 compared to 1 M x 4 (PTH and SMT)

      The following table compares the pin assignments of the two
chips.  The accepted industry abbreviations for DRAM functions are
used.

      PTH Pin No.    SMT Pin No.    1Mbit     4Mbit
      1              1         I/O 1     I/O 1
      2              2         I/O 2     I/O 2
      3              3         WE        WE
      4              4         RAS       RAS
      5              5         NC        A9        *****
      6              9         A0        A0
      7             10         A1        A1
      8             11         A2        A2
      9             12         A3        A3
     10             13         VDD       VDD
     11             14         A4        A4
     12             15         A5        A5
     13             16         A6        A6
     14             17         A7        A7
     15             18         A8        A8
     16             22         OE        OE
     17             23         CAS       CAS
     18             24         I/O 3     I/O 3
     19             25         I/O 4     I/O 4
     20             26         VSS       VSS.
The only difference arises with pin 5.  The 4Mbit chip uses this for
the high order address line - the 1Mbit chip has no connection to
this pin.
1M x 1 Compared to 4M...