Browse Prior Art Database

Microcode POS Register Implementation

IP.com Disclosure Number: IPCOM000121305D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 4 page(s) / 130K

Publishing Venue

IBM

Related People

Buckland, PA: AUTHOR [+2]

Abstract

The Programmable Option Select (POS) registers on Micro Channel* cards are ordinarily implemented as a separate EPROM containing the card Vital Product Data (VPD) and having specialized hardware gating to the Micro Channel data buses. In order to eliminate the separate EPROM, the VPD source is moved into the initial program load (IPL) ROS, the POS registers implemented in RAM and a specialized microcode routine written to take the place of the usual hardware gating to the Micro Channel buses.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Microcode POS Register Implementation

      The Programmable Option Select (POS) registers on Micro
Channel* cards are ordinarily implemented as a separate EPROM
containing the card Vital Product Data (VPD) and having specialized
hardware gating to the Micro Channel data buses.  In order to
eliminate the separate EPROM, the VPD source is moved into the
initial program load (IPL) ROS, the POS registers implemented in RAM
and a specialized microcode routine written to take the place of the
usual hardware gating to the Micro Channel buses.

      Fig. 1 is the usual POS register implementation.  The POS
registers 1 are a read/write array of hardware registers.  Registers
0 and 1 have fixed contents (the card ID).  Gate 4 connects the POS
registers to the Micro Channel.  The registers are disconnected at
power on and are connected when the processor or card logic
determines that the card is working correctly.  POS6 and POS7 are
gated to an indirect address generator 2 that addresses the EPROM 3.
The indirect address generator is designed to gate zeroes to POS3
whenever the indirect address exceeds the bounds of the VPD in the
EPROM.

      Fig. 2 is the new implementation.  The POS registers 11 are
implemented as part of the RAM 10 in the chips connecting to the
Micro Channel.  These registers are cleared as part of the card Power
on  Reset, thus presenting all zeroes to the Micro Channel.  This
reset has the same effect as disabling gate 4 in the hardware
implementation.

      When the card IPL is finished, the microprocessor writes the
card ID into POS0 and POS1; the same effect as enabling gate 4 in the
hardware version.

      When the host reads the POS registers, the microprocessor is
not involved (i.e., the registers are read from the RAM to the host
without processor involvement).

      When the host writes any POS register, the address trap logic
12 detects the access and writes the low-order 3 bits of the POS
register address into register 15.  The hardware then sets the
not_ready latch 16 and interrupts microprocessor 14 at the highest
functional interrupt level. If the access was to a register which is
read only to the host, address trap logic 12 suppresses the write
pulse to RAM 10 and, thus, prevents the register from being changed.

      The not_ready latch stops the Micro Channel to wait for the
microcode action; the same Micro Channel waiting action that occurs
with slow logic cards.

      The address trap logic inte...