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Merged Hold/ Increment Function

IP.com Disclosure Number: IPCOM000121311D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 75K

Publishing Venue

IBM

Related People

Weinberger, A: AUTHOR

Abstract

An incrementer is implemented with an XOR function per bit position. When applied to a register that also requires a HOLD (i.e., retain the register content for the next cycle), the HOLD can be merged with the incrementer into a single XOR function per bit position, so that only a single port to a register bit is needed for the combined function.

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Merged Hold/ Increment Function

      An incrementer is implemented with an XOR function per
bit position.  When applied to a register that also requires a HOLD
(i.e., retain the register content for the next cycle), the HOLD can
be merged with the incrementer into a single XOR function per bit
position, so that only a single port to a register bit is needed for
the combined function.

      The gating conditions for HOLD must be mutually exclusive with
the conditions for incrementing, which is usually the case.

      Fig. 1 shows standard two-port SRLs (Shift Register Latches)
for the hold and increment functions of a byte with parity.  Fig. 2
derives the expressions that merge the HOLD into the increment
function, and Fig. 3 shows the resulting one-port merged function.

      The HOLD function can be similarly merged into a decrement
function.