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FPU Divide Result Register Implementation

IP.com Disclosure Number: IPCOM000121314D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Elliott, TA: AUTHOR [+3]

Abstract

This Floating Point uses a Radix-4 non-restoring division algorithm. In this implementation, two bits of the quotient are calculated each clock cycle and stored in a register. In most implementations, this requires a dedicated 55-bit shift register (53 bit significant plus Guard and Round bits). With the severe space restrictions for the Floating Point, we needed to modify existing hardware to perform the function without overly complicating the design.

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This is the abbreviated version, containing approximately 91% of the total text.

FPU Divide Result Register Implementation

      This Floating Point uses a Radix-4 non-restoring division
algorithm.  In this implementation, two bits of the quotient are
calculated each clock cycle and stored in a register. In most
implementations, this requires a dedicated 55-bit shift register (53
bit significant plus Guard and Round bits).  With the severe space
restrictions for the Floating Point, we needed to modify existing
hardware to perform the function without overly complicating the
design.

      By using the existing Normalize register, the divide
intermediate result can be sampled and iterated on the feedback path,
from the rounder back to the Normalize register.  The 2-bit divide
result is computed and put into the Normalize register.  For the next
iteration of the result, the intermediate result is shifted two
digits left, and the new 2-bit result is appended on the end.  This
process is continued until the complete result is calculated.  See
Fig. 1.

      When not operating on the divide instruction, the 2-bit shift
is not performed and the 2:1 mux is selected to use the feedback
data.  This allows for additional normalization and special case
feedback to occur.

      Since the normalize register is much larger than the need of
the divide result, it is used as in Fig. 2.

      At the end of the divide operations, the complete normalized
mantissa is in the Normalize register.

      By using the existing normalize register...