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Fast Counter and Comparator for Data Transfers

IP.com Disclosure Number: IPCOM000121319D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 125K

Publishing Venue

IBM

Related People

Brodnax, T: AUTHOR [+3]

Abstract

The parallel transfer of data has enhanced the overall system performance of recently designed machines. This transfer can either be the result of multiple transfer instructions, Direct Memory Access (DMA) channels or I/O commands. The instructions or DMA commands may specify a number of words to transfer or a starting and ending address for the words to be shared. These multiple transfers present a unique problem for the logic which controls the address and data ports involved. There are many factors which may prevent a transfer of the maximum possible number of words. Some architectures require that multiple transfers have addressing restrictions. For instance, if four transfers are possible, some architectures would transfer words based on the address LSBs.

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Fast Counter and Comparator for Data Transfers

      The parallel transfer of data has enhanced the overall
system performance of recently designed machines.  This transfer can
either be the result of multiple transfer instructions, Direct Memory
Access (DMA) channels or I/O commands.  The instructions or DMA
commands may specify a number of words to transfer or a starting and
ending address for the words to be shared.  These multiple transfers
present a unique problem for the logic which controls the address and
data ports involved.  There are many factors which may prevent a
transfer of the maximum possible number of words.  Some architectures
require that multiple transfers have addressing restrictions.  For
instance, if four transfers are possible, some architectures would
transfer words based on the address LSBs.  Another obvious transfer
limitation would exist if a transfer is supposed to come from a
buffer which does not have enough words for a maximum transfer or
into a buffer which does not have enough empty locations.  The logic
which determines the number of words to be transferred may have a
long delay. This logic is then used to determine if a transfer is
complete (if the DMA command or transfer instruction has been
completed) - a potentially unacceptable path.

      As described above, it is common for a multiple transfer
instruction or a DMA command to specify the number of words to be
transferred.  It is then necessary to monitor the transfers to ensure
that the complete number of transfers has taken place.  The two basic
equations which monitor the multiword transfer of a particular
implementation are:
BYTE_CNT is holding the desired number of bytes to be transferred by
the current instruction.  BT_TRANS holds the number of bytes
transferred so far, and that number will be incremented by INC_BC.
TERM_TRANS indicates that the transfer instruction should be
terminated after the transfer in progress because the total number of
specified bytes has been transferred.  Assuming that the control
logic takes a significant portion of the cycle time to generate
INC_BC, it will be difficult to pass through the 8-bit adder and the
8-bit comparator in the remaining portion of the cycle.

      The solution reached for this critical timing path is based on
the Conditional-Sum Adder algorithm.  Remember that in the algorithm
the more significant bits go into two adders - one with no carry
assumed and the other has a carry assumed.  The carry from the less
significant bits...