Browse Prior Art Database

Novel SRAM Datapath Architecture and Circuit Using Local Read-bus

IP.com Disclosure Number: IPCOM000121320D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Gabillard, B: AUTHOR [+4]

Abstract

In high density SRAM, the design of the datapath is a key point to obtain fast access time.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 89% of the total text.

Novel SRAM Datapath Architecture and Circuit Using Local Read-bus

      In high density SRAM, the design of the datapath is a key
point to obtain fast access time.

      The present invention proposes a new datapath architecture
which improve the bitlines discharging slew rate; thus, the RAM
sensing speed is boosted.

      The idea consists of reducing the capacitance of the I/O lines.
Since the capacitance becomes smaller, the RC time constants smaller,
the discharging speed increases.

      This approach is implemented by creating a local read-bus,
which is an additional multiplex at the first sense-amplifier level.
This sense-amplifier multiplex (SAMUX) selects 1/p I/O lines.  Since
the bitswitches (BS) select 1/m columns,  BS+SAMUX selects 1/(mxp)
columns.

      To select 1/n columns, the prior approach needs n wires to
perform the multiplex/bit decoding function, while the new appoach
needs m+p wires. Thus, the new approach will save chip area.

      Fig. 1 shows the new architecture and Fig. 2 the SAMUX circuit
schematic.

      The SAMUX circuit is composed of two parts: AMP and MUX. AMP is
a NMOS cross-coupled amplifier built with 3 devices (T5,T6,T7). MUX
is composed of 4 devices; T1,T2 are NMOS source follower, and T3,T4
act as switches. AMP is unique for a sub-array, MUX is repeated as
many times as the multiplex required (p times in the above example).
However, it does not cost extra area; the MUX devices are easily laid
out un...