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Fast Multiplexing Structure for Increment/ Nonincrement/ Special in this Floating Point

IP.com Disclosure Number: IPCOM000121321D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Karim, FO: AUTHOR [+2]

Abstract

This floating point implements its special-case number handling totally in the control circuitry, bypassing the data flow to maintain simplicity. At the bottom of the data flow, the result produced in the dataflow must be multiplexed with the special-case results produced in the control logic. Given the severe space restriction and an aggressive cycle time, simply sticking a mux below the normal dataflow was unacceptable. Our goal was to find an alternative design which would provide this required muxing function, while not significantly adding circuits or slowing down the dataflow.

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Fast Multiplexing Structure for Increment/ Nonincrement/ Special
in this Floating Point

      This floating point implements its special-case number
handling totally in the control circuitry, bypassing the data flow to
maintain simplicity.  At the bottom of the data flow, the result
produced in the dataflow must be multiplexed with the special-case
results produced in the control logic.  Given the severe space
restriction and an aggressive cycle time, simply sticking a mux below
the normal dataflow was unacceptable.  Our goal was to find an
alternative design which would provide this required muxing function,
while not significantly adding circuits or slowing down the dataflow.

      Fig. 1 shows the most straightforward solution to the problem.
That is to increment the data flow result and then mux in the special
result data.  The problem is this design is too large and slow.  The
reason this design is slow and large is serialization of work done by
using these standard off-the-shelf macros to first increment and then
mux the special data.

      Looking at the internal circuity of the OTS Incrementer (See
Fig.  2), the potential for size reduction and performance
improvement becomes apparent.

      By combining the 2:1 mux inside the OTS Incrementer with the
2:1 mux placed at the bottom of the dataflow, we have obtained both
goals.

      The design will provide a size reduction over Fig. 1. Two 2:1
muxes consume 12 transistors while a single 3...