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Most Significant Bit Detector

IP.com Disclosure Number: IPCOM000121324D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Weinberger, A: AUTHOR

Abstract

Fig. 1 shows the truth table for the most significant one detector of a 32-bit word, A. The output, B, is the address of the most significant (left-most) one. The equations for the outputs or their complements may optionally include don't care terms that permit sharing subfunctions among the outputs.

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Most Significant Bit Detector

      Fig. 1 shows the truth table for the most significant one
detector of a 32-bit word, A.  The output, B, is the address of the
most significant (left-most) one.  The equations for the outputs or
their complements may optionally include don't care terms that permit
sharing subfunctions among the outputs.

      Consider the complement outputs of the two low-order outputs,
B5 and B4, divided into 4-bit group functions.
B5 = G2 + A3x.G6 + ... + A27x.G30 + A31x
      0    0   4          0    28    28
B4 = A1 + A3#.A5 + ... + A27#.A29 + A31
      0    0   4          0    28    0
where Aj = Ai + Ai+1 + ... + Aj,
        i
       Gi+2 = Ai + Ai+1.Ai+2 = Ai + Ai+1 .Ai+2 noting that Ai is a
don't
             i           i care term,
       A0ix means every even numbered A is a don't care term (A0,A2,
etc.), and
       Ai     means A1,A6, etc., are don't care terms.
        0         0  4
Using Ai+1 instead of Ai+1 in implementing G permits Ai+1 to be used
       i                                              i for both B5
and B4.

      Figs. 2 and 3 illustrate the comparison for a 4-bit macro of
the detector using CSEF (current switch emitter follower) logic.