Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
This article describes a mechanism consisting of two 16-bit timers that may be operated independently of each other or concatenated to form a 32-bit timer and providing for three different types of outputs from each timer.
describes a mechanism consisting of two
16-bit timers that may be operated independently of each other or
concatenated to form a 32-bit timer and providing for three different
types of outputs from each timer.
The 16-bit timers disclosed herein are
designated the low and
high timers as related to their significance when in a 32-bit
configuration. Each timer consists of a 16-bit count register that
begins its count at zero and counts up by one every four cycles and a
16-bit compare register with a comparator to determine when the
compare register value is equal to the count register value. When
the two values compare, a compare latch is set, the specified output
function is performed and the count register reset to zero and
counting continues as before. An incrementer is included with the
The figure is
a functional block diagram of the two timers plus
a 4 to 1 multiplexer (mux) and a hold register that are used to read
the values contained in the four timer registers.
timers are concatenated to form a 32-bit timer, the
low compare latch acts like a carry to the high timer which is
stepped one count for each low timer compare. When both high and low
compare latches are set, the desired output function will be done and
both count registers reset to zero.
functions are provided for each timer. First, if
enabled, each compare latch will set an interrupt for the
microprocessor. Second, one I/O pin is provided for each timer and
one of two functions are provided on the I/O pins. These functions
are (a) a pulse when a compare is realized or (b) a toggle function
that will produce a square wave which changes state each time a
compare is made.
a 16-bit 4 to 1 mux and a hold register is
provided so that the contents of the high and low count registers and